Patents by Inventor Richard Hammond

Richard Hammond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030234439
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Application
    Filed: June 25, 2002
    Publication date: December 25, 2003
    Applicant: AmberWave Systems Corporation
    Inventors: Matthew T. Currie, Richard Hammond
  • Publication number: 20030227057
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Application
    Filed: October 4, 2002
    Publication date: December 11, 2003
    Inventors: Anthony J. Lochtefeld, Thomas A. Langdo, Richard Hammond, Matthew T. Currie, Eugene A. Fitzgerald
  • Publication number: 20030207571
    Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
    Type: Application
    Filed: April 23, 2003
    Publication date: November 6, 2003
    Applicant: Amberwave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Richard Hammond, Matthew Currie
  • Publication number: 20030121087
    Abstract: A new variety of Chrysanthemum plant named ‘Esperanto,’ having a good uniform canopy of bright purple/white bi-colored single flowers with a yellow/green disc. The new variety has medium vigor with a free branching and uniform spreading habit and good foliage presentation.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Inventor: Richard Hammond
  • Patent number: 6583015
    Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1−xGex layer on a substrate, a strained channel layer on the relaxed Si1−xGex layer, and a Si1−yGey layer; removing the Si1−yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
    Type: Grant
    Filed: August 6, 2001
    Date of Patent: June 24, 2003
    Assignee: AmberWave Systems Corporation
    Inventors: Eugene A. Fitzgerald, Richard Hammond, Matthew Currie
  • Publication number: 20030102498
    Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.
    Type: Application
    Filed: September 24, 2002
    Publication date: June 5, 2003
    Inventors: Glyn Braithwaite, Richard Hammond, Matthew Currie
  • Publication number: 20030057416
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Application
    Filed: September 20, 2002
    Publication date: March 27, 2003
    Applicant: AmberWave Systems Corporation
    Inventors: Matthew Currie, Anthony Lochtefeld, Richard Hammond, Eugene Fitzgerald
  • Publication number: 20030049893
    Abstract: A method is disclosed for isolating device regions in a heterostructure that includes at least one layer of a strained semiconductor material. The method includes the steps of forming a trench in the at least one layer of strained semiconductor material using an etch chemistry that is selected to etch different layers of said heterostructure sufficiently similarly that said trench includes walls that are substantially straight, and depositing a dielectric material in the trench.
    Type: Application
    Filed: June 7, 2002
    Publication date: March 13, 2003
    Inventors: Matthew Currie, Richard Hammond
  • Publication number: 20030013323
    Abstract: A method is disclosed of forming buried channel devices and surface channel devices on a heterostructure semiconductor substrate. In an embodiment, the method includes the steps of providing a structure including a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate wherein the first oxidation rate is greater than the second oxidation rate, reacting said first layer to form a sacrificial layer, and removing said sacrificial layer to expose said second layer.
    Type: Application
    Filed: June 14, 2002
    Publication date: January 16, 2003
    Inventors: Richard Hammond, Matthew Currie
  • Publication number: 20020125475
    Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.
    Type: Application
    Filed: November 20, 2001
    Publication date: September 12, 2002
    Inventors: Jack Oon Chu, Richard Hammond, Khalid Ezzeldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
  • Publication number: 20020104993
    Abstract: A semiconductor structure including a relaxed Si1−xGex layer on a substrate, a strained channel layer on said relaxed Si1−xGex layer, and a sacrificial Si1−yGey layer. The sacrificial Si1−yGey layer is removed before providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the structure includes a Si1−yGey spacer layer and a Si layer.
    Type: Application
    Filed: August 6, 2001
    Publication date: August 8, 2002
    Inventors: Eugene A. Fitzgerald, Richard Hammond, Matthew Currie
  • Publication number: 20020068393
    Abstract: A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer, and a Si1-yGey layer; removing the Si1-yGey layer; and providing a dielectric layer. The dielectric layer includes a gate dielectric of a MISFET. In alternative embodiments, the heterostructure includes a SiGe spacer layer and a Si layer.
    Type: Application
    Filed: August 6, 2001
    Publication date: June 6, 2002
    Inventors: Eugene A. Fitzgerald, Richard Hammond, Matthew Currie
  • Patent number: 6350993
    Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: February 26, 2002
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
  • Patent number: 6221222
    Abstract: The present invention provides a reference electrode solution containing ammonium salts and phosphonium salts for the potentiometric measurement of pH and method of using the same. The use of the ammonium salts and the phosphonium salts to replace potassium chloride or sodium chloride as reference electrolytes in a standard reference electrode minimizes the formation of precipitates in sample solutions containing cation-sensitive compounds. Disruption of ion flow through the reference electrode is eliminated, and accurate pH measurements may be obtained in solutions that contain compounds having a strong affinity for hard cations.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: April 24, 2001
    Assignee: Baxter International Inc.
    Inventors: James Kipp, Glenn Wehrmann, Richard Hammond, Christine Rebbeck