Patents by Inventor Richard Schultz

Richard Schultz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7420229
    Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a manufacturing process. The cells can be configured to operate as ring oscillators increasing the effective circuit frequency of the test module allowing higher frequency circuit testing, and shortening the time it takes to perform life cycle testing. Visibly marking cells, combined with electrically isolating error prone circuit segments makes, identifying defects much more efficient. The accessibility of many testing methods allows quick location of root cause failures, which allows improvements to be made to the manufacturing process.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: September 2, 2008
    Assignee: LSI Corporation
    Inventors: Richard Schultz, Michael Schmidt
  • Patent number: 7370257
    Abstract: A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix format and connected so that they may be tested along rows or columns. When a failure along a specific row and a specific column is identified, the process test circuit at the intersection may be identified as the failure point.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: May 6, 2008
    Assignee: LSI Logic Corporation
    Inventors: Richard Schultz, Gerald Shipley, Derryl Allman
  • Publication number: 20080019277
    Abstract: A personal computer's (PC) microprocessor is used to provide both the physical layer (PHY) and media access control (MAC) processing functions required to implement a wireless local area network (WLAN) adapter. This technique uses the polling mechanism associated with the power save (PS) functionality of WLAN protocol to relieve networking stress on the host processing system. It does this while maintaining networking integrity and packet delivery. The WLAN protocol polling mechanism is used to briefly inhibit the transfer of packets from the WLAN access point (AP) during peak periods of network traffic and/or host processor loading. Because the modulation, demodulation, and MAC functions, typically implemented in dedicated hardware on existing adapters are implemented in software running on the host PC microprocessor, other host system processes and applications can interfere with these time critical functions.
    Type: Application
    Filed: August 15, 2007
    Publication date: January 24, 2008
    Applicant: CONEXANT SYSTEMS, INC.
    Inventors: Richard Schultz, George Nelson, John Hoffmann
  • Patent number: 7308627
    Abstract: A test vehicle a system and method for evaluating an interconnect module manufacturing process while dynamically testing performance with high-speed operational frequencies is disclosed. The test vehicle incorporates a self-timed or gated speed circuit that can detect subtle resistive faults and also show the exact location in the array where the speed fault occurred based on test program data logs from scan flip flops. One embodiment incorporates a gated clock in the gated speed circuit producing gated data that delivers greater statistical properties with respect to Integrated Circuit Direct Drain Quiescent Current (IDDQ) testing.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: December 11, 2007
    Assignee: LSI Corporation
    Inventors: Richard Schultz, Derryl Allman, Jan Fure
  • Patent number: 7284213
    Abstract: A system and method for collecting and analyzing optical inspection results obtained during the manufacturing process and comparing those results to actual functional results of a specially designed test vehicle integrated circuit. The test vehicle integrated circuit allows failures to be localized to very small areas, which allows more accurate correlation between inspection faults and functional failures. The correlation of inspection faults to actual functional failures is used to change the sensitivity settings for an optical inspection system to more accurately detect defects that are likely to be functional failures.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: October 16, 2007
    Assignee: LSI Corporation
    Inventors: Jan Fure, Richard Schultz, Derryl Allman
  • Patent number: 7222548
    Abstract: A black panel assembly for use in an accelerated weathering test device having a specimen table includes a platform disposed on the specimen table, the platform including a plurality of standoffs and a mounting surface, wherein the plurality of standoffs elevate the mounting surface relative to the specimen table. The black panel assembly additionally includes a black panel having an exposure side and a mounting side, wherein the black panel is mounted on the platform from the mounting side. The black panel assembly further includes a temperature sensor connected to the exposure side of the black panel.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: May 29, 2007
    Assignee: Atlas Material Testing Technology, L.L.C.
    Inventors: Chris Wass, Richard Schultz, Mikhail Rokhlenko
  • Publication number: 20070015297
    Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a manufacturing process. The cells can be configured to operate as ring oscillators increasing the effective circuit frequency of the test module allowing higher frequency circuit testing, and shortening the time it takes to perform life cycle testing. Visibly marking cells, combined with electrically isolating error prone circuit segments makes, identifying defects much more efficient. The accessibility of many testing methods allows quick location of root cause failures, which allows improvements to be made to the manufacturing process.
    Type: Application
    Filed: September 25, 2006
    Publication date: January 18, 2007
    Inventors: Richard Schultz, Michael Schmidt
  • Patent number: 7154734
    Abstract: A linear capacitor design providing shielding on all sides of the linear capacitor. In one aspect the capacitor provides a signal side metal layer substantially enclosed by a dielectric material which is, in turn, substantially enclosed by an upper and lower metal shield layer. in another aspect, the upper and lower shield metal layers may be coupled by a plurality of vias. In another aspect, a plurality of alternating intermediate layers provide signal side metal and shield metal separated by dielectric material such that each signal side layer is substantially enclosed by one or more shield metal layers. In another aspect, multiple intermediate signal side metal layers are conductively coupled to one another by a plurality of vias and multiple shield metal layers are conductively coupled to one another by a plurality of vias.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: December 26, 2006
    Assignee: LSI Logic Corporation
    Inventors: Richard Schultz, Jeffrey Burleson, Steven Howard
  • Publication number: 20060251782
    Abstract: The food presentation plank is an elongate, planar plank used in the transport of food from the preparation location to the location of presentation for consumption. The plank has handles formed in the ends of the plank, the handles also being dimensioned and configured to receive condiment or sauce dishes. The plank has a liquid collection groove surrounding the food presentation portion of the plank, for collection of liquids coming from food on the plank. This groove eliminates the need for a dam or wall for preventing liquid dripping, and without interfering with the full view of the presentation on the plank. The plank allows a user to prepare for the attractive and appetizing presentation of a catered or gourmet meal in a location remote from that of either the presentation or consumption.
    Type: Application
    Filed: May 4, 2006
    Publication date: November 9, 2006
    Inventor: Richard Schultz
  • Patent number: 7129101
    Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a manufacturing process. The cells can be configured to operate as ring oscillators increasing the effective circuit frequency of the test module allowing higher frequency circuit testing, and shortening the time it takes to perform life cycle testing. Visibly marking cells, combined with electrically isolating error prone circuit segments makes, identifying defects much more efficient. The accessibility of many testing methods allows quick location of root cause failures, which allows improvements to be made to the manufacturing process.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: October 31, 2006
    Assignee: LSI Logic Corporation
    Inventors: Richard Schultz, Michael Schmidt
  • Publication number: 20060242522
    Abstract: A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix format and connected so that they may be tested along rows or columns. When a failure along a specific row and a specific column is identified, the process test circuit at the intersection may be identified as the failure point.
    Type: Application
    Filed: April 8, 2005
    Publication date: October 26, 2006
    Applicant: LSI Logic Corporation
    Inventors: Richard Schultz, Gerald Shipley, Derryl Allman
  • Publication number: 20060226847
    Abstract: A system and method for collecting and analyzing optical inspection results obtained during the manufacturing process and comparing those results to actual functional results of a specially designed test vehicle integrated circuit. The test vehicle integrated circuit allows failures to be localized to very small areas, which allows more accurate correlation between inspection faults and functional failures. The correlation of inspection faults to actual functional failures is used to change the sensitivity settings for an optical inspection system to more accurately detect defects that are likely to be functional failures.
    Type: Application
    Filed: October 11, 2005
    Publication date: October 12, 2006
    Applicant: LSI Logic Corporation
    Inventors: Jan Fure, Richard Schultz, Derryl Allman
  • Publication number: 20060207352
    Abstract: A black panel assembly for use in an accelerated weathering test device having a specimen table includes a platform disposed on the specimen table, the platform including a plurality of standoffs and a mounting surface, wherein the plurality of standoffs elevate the mounting surface relative to the specimen table. The black panel assembly additionally includes a black panel having an exposure side and a mounting side, wherein the black panel is mounted on the platform from the mounting side. The black panel assembly further includes a temperature sensor connected to the exposure side of the black panel.
    Type: Application
    Filed: March 17, 2005
    Publication date: September 21, 2006
    Inventors: Chris Wass, Richard Schultz, Mikhail Rokhlenko
  • Publication number: 20060162277
    Abstract: A method of constructing an interlocking corner joint by combining fixed or variable sized interlocking fingers from at least two sides, full or partial feed though dowel pegs or other geometrically shaped pegs, finishing nails, pins or screws and glue or epoxy at the interface of the interlocking fingers and pegs and pins. The resulting interlocking corner joint is much stronger than a standard dovetail joint or box finger joint due to the increased surface area created by the holes, pegs and pins. Due to the interlocking fingers, holes, pegs and pins, the interlocking corner joint will not pull apart in any one dimension x,y,z in the event that the glue joint fails.
    Type: Application
    Filed: April 30, 2005
    Publication date: July 27, 2006
    Inventor: Richard Schultz
  • Publication number: 20060125305
    Abstract: An interior weld for furniture having a tubular member is disclosed. The weld has a first tubular member and a second tubular member. The first tubular member is adapted to receive the tubular second member. An edge of the tubular second member contacts an inner surface of the first tubular member. A weld is formed on the inner surface of the first tubular member at the contact point where the second tubular member contacts the first tubular member. There is a weld at that contact point which immovably attaches the second member to the first member.
    Type: Application
    Filed: February 3, 2006
    Publication date: June 15, 2006
    Inventors: Richard Schultz, Peter Schultz
  • Publication number: 20060129859
    Abstract: Exemplary techniques for turning off the clock signal to flip flops are described, which may reduce power consumption by electronic devices. In an implementation, a clock-gating logic turns off the clock signal to a flip flop when a data input of the flip flop remains untoggled. The reduction in power consumption is envisioned to also reduce heat generation.
    Type: Application
    Filed: December 13, 2004
    Publication date: June 15, 2006
    Inventor: Richard Schultz
  • Publication number: 20060123377
    Abstract: A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using a layout tool that produces a layout verses schematic reference file, mapping the reference file to the net list to create a mapping file, and analyzing the mapping file to verify that the layout meets various criteria. Each block may be verified using simulation tools that are appropriate for that piece of the overall circuit, and using conditions that may maximize the strain on the circuit. The results from the simulations are compared to the physical layout to determine if the physical layout is able to properly conduct the electrical signals.
    Type: Application
    Filed: December 7, 2004
    Publication date: June 8, 2006
    Applicant: LSI Logic Corporation
    Inventors: Richard Schultz, Robert Waldron, Norman Mause, Larry Greenhouse
  • Publication number: 20060076972
    Abstract: An integrated circuit is provided, which includes a transistor device under test, an AC drive circuit, an AC bias circuit and a DC bias circuit. The AC drive circuit generates an AC drive signal. The AC bias circuit biases the transistor device under AC bias conditions in response to the AC drive signal. The DC bias circuit biases the transistor device under DC bias conditions. A switch circuit selectively couples the transistor device to the AC bias circuit in an AC stress mode and to the DC bias circuit in a DC measurement mode.
    Type: Application
    Filed: October 11, 2004
    Publication date: April 13, 2006
    Applicant: LSI Logic Corporation
    Inventors: John Walker, SangJune Park, Richard Schultz
  • Patent number: 7023252
    Abstract: A signal deskew circuit is provided, which includes first and second signal branches, each branch extending between a start location and a respective end location. Each signal branch includes a send path and a return path, which have substantially the same propagation delays. An adjustable delay buffer is coupled in the send and return paths of a first of the signal branches and has a delay, which is adjustable based on a respective adjust signal. A skew sensor coupled to the return paths of the first and second signal branches, which generates the respective adjust signal for the adjustable delay buffer based on a phase difference between signals on the return paths of the first and second signal branches.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: April 4, 2006
    Assignee: LSI Logic Corporation
    Inventor: Richard Schultz
  • Patent number: D554916
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: November 13, 2007
    Inventor: M. Richard Schultz