Patents by Inventor Richard Schultz

Richard Schultz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060125305
    Abstract: An interior weld for furniture having a tubular member is disclosed. The weld has a first tubular member and a second tubular member. The first tubular member is adapted to receive the tubular second member. An edge of the tubular second member contacts an inner surface of the first tubular member. A weld is formed on the inner surface of the first tubular member at the contact point where the second tubular member contacts the first tubular member. There is a weld at that contact point which immovably attaches the second member to the first member.
    Type: Application
    Filed: February 3, 2006
    Publication date: June 15, 2006
    Inventors: Richard Schultz, Peter Schultz
  • Publication number: 20060123377
    Abstract: A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using a layout tool that produces a layout verses schematic reference file, mapping the reference file to the net list to create a mapping file, and analyzing the mapping file to verify that the layout meets various criteria. Each block may be verified using simulation tools that are appropriate for that piece of the overall circuit, and using conditions that may maximize the strain on the circuit. The results from the simulations are compared to the physical layout to determine if the physical layout is able to properly conduct the electrical signals.
    Type: Application
    Filed: December 7, 2004
    Publication date: June 8, 2006
    Applicant: LSI Logic Corporation
    Inventors: Richard Schultz, Robert Waldron, Norman Mause, Larry Greenhouse
  • Publication number: 20060076972
    Abstract: An integrated circuit is provided, which includes a transistor device under test, an AC drive circuit, an AC bias circuit and a DC bias circuit. The AC drive circuit generates an AC drive signal. The AC bias circuit biases the transistor device under AC bias conditions in response to the AC drive signal. The DC bias circuit biases the transistor device under DC bias conditions. A switch circuit selectively couples the transistor device to the AC bias circuit in an AC stress mode and to the DC bias circuit in a DC measurement mode.
    Type: Application
    Filed: October 11, 2004
    Publication date: April 13, 2006
    Applicant: LSI Logic Corporation
    Inventors: John Walker, SangJune Park, Richard Schultz
  • Patent number: 7023252
    Abstract: A signal deskew circuit is provided, which includes first and second signal branches, each branch extending between a start location and a respective end location. Each signal branch includes a send path and a return path, which have substantially the same propagation delays. An adjustable delay buffer is coupled in the send and return paths of a first of the signal branches and has a delay, which is adjustable based on a respective adjust signal. A skew sensor coupled to the return paths of the first and second signal branches, which generates the respective adjust signal for the adjustable delay buffer based on a phase difference between signals on the return paths of the first and second signal branches.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: April 4, 2006
    Assignee: LSI Logic Corporation
    Inventor: Richard Schultz
  • Publication number: 20060068054
    Abstract: TDF testing has become a requirement for any and all product applications for which product quality is of utmost concern, e.g. storage components. The specific problem with regard to TDF testing is that most production test systems cannot exceed a 200 Mhz effective TDF test rate. A higher speed solution for use with existing tester platforms is provided, without having to spend significant capital resources to upgrade to newer tester platforms. One solution adds circuitry to the test hardware used to interface to the DUT. Another solution adds circuitry to the actual design prior to releasing it for processing.
    Type: Application
    Filed: September 30, 2004
    Publication date: March 30, 2006
    Inventors: Kevin Gearhardt, Richard Schultz
  • Publication number: 20060061935
    Abstract: A linear capacitor design providing shielding on all sides of the linear capacitor. In one aspect the capacitor provides a signal side metal layer substantially enclosed by a dielectric material which is, in turn, substantially enclosed by an upper and lower metal shield layer. in another aspect, the upper and lower shield metal layers may be coupled by a plurality of vias. In another aspect, a plurality of alternating intermediate layers provide signal side metal and shield metal separated by dielectric material such that each signal side layer is substantially enclosed by one or more shield metal layers. In another aspect, multiple intermediate signal side metal layers are conductively coupled to one another by a plurality of vias and multiple shield metal layers are conductively coupled to one another by a plurality of vias.
    Type: Application
    Filed: September 20, 2004
    Publication date: March 23, 2006
    Inventors: Richard Schultz, Jeffrey Burleson, Steven Howard
  • Patent number: 7008021
    Abstract: An interior weld for furniture having a tubular member is disclosed. The weld has a first tubular member and a second tubular member. The first tubular member is adapted to receive the tubular second member. An edge of the tubular second member contacts an inner surface of the first tubular member. A weld is formed on the inner surface of the first tubular member at the contact point where the second tubular member contacts the first tubular member. There is a weld at that contact point which immovably attaches the second member to the first member.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: March 7, 2006
    Inventors: Richard Schultz, Peter Schultz
  • Publication number: 20050258881
    Abstract: A signal deskew circuit is provided, which includes first and second signal branches, each branch extending between a start location and a respective end location. Each signal branch includes a send path and a return path, which have substantially the same propagation delays. An adjustable delay buffer is coupled in the send and return paths of a first of the signal branches and has a delay, which is adjustable based on a respective adjust signal. A skew sensor coupled to the return paths of the first and second signal branches, which generates the respective adjust signal for the adjustable delay buffer based on a phase difference between signals on the return paths of the first and second signal branches.
    Type: Application
    Filed: May 19, 2004
    Publication date: November 24, 2005
    Applicant: LSI Logic Corporation
    Inventor: Richard Schultz
  • Publication number: 20050200189
    Abstract: An interior weld for furniture having a tubular member is disclosed. The weld has a first tubular member and a second tubular member. The first tubular member is adapted to receive the tubular second member. An edge of the tubular second member contacts an inner surface of the first tubular member. A weld is formed on the inner surface of the first tubular member at the contact point where the second tubular member contacts the first tubular member. There is a weld at that contact point which immovably attaches the second member to the first member.
    Type: Application
    Filed: March 12, 2004
    Publication date: September 15, 2005
    Inventors: Richard Schultz, Peter Schultz
  • Publication number: 20050109180
    Abstract: The combination of a base, with which at least one sheet layer can be operatively supported to be cut, a guide assembly, and a cutting blade assembly. The cutting blade assembly includes first and second cutting blades. The cutting blade assembly is selectively changeable between a) a first state wherein the first cutting blade is in a first operative position and the second cutting blade is in a first inactive position, and b) a second state wherein the second cutting blade is in a second operative position and the first cutting blade is in a second inactive position. The cutting blade assembly cooperates with the guide assembly to be movable guidingly in a cutting path. The first cutting blade in the first operative position causes cutting of a sheet layer operatively supported on the base as the cutting blade assembly is moved in the cutting path.
    Type: Application
    Filed: November 20, 2003
    Publication date: May 26, 2005
    Inventors: Richard Schultz, Keith Alsberg, Eric Wilmot
  • Publication number: 20050114811
    Abstract: A system and method for evaluating multiple corner case static timing analyses. For each node within the analysis, the variability and margin of the node is used to create a risk factor that is used to identify nodes for further analysis. In some cases, a subset of nodes may be selected for static timing analysis with several additional corner cases. The variability of the node may be determined by the difference between the maximum and minimum value of the node between corner case analyses. The margin may be determined by the difference between the actual timing and the required timing. Various ratios using variability and margin may be used to identify those nodes on which to perform further analysis.
    Type: Application
    Filed: January 3, 2005
    Publication date: May 26, 2005
    Applicant: LSI Logic Corporation
    Inventor: Richard Schultz
  • Publication number: 20050105671
    Abstract: An automatically scramming nuclear reactor system. One embodiment comprises a core having a coolant inlet end and a coolant outlet end. A cooling system operatively associated with the core provides coolant to the coolant inlet end and removes heated coolant from the coolant outlet end, thus maintaining a pressure differential therebetween during a normal operating condition of the nuclear reactor system. A guide tube is positioned within the core with a first end of the guide tube in fluid communication with the coolant inlet end of the core, and a second end of the guide tube in fluid communication with the coolant outlet end of the core. A control element is positioned within the guide tube and is movable therein between upper and lower positions, and automatically falls under the action of gravity to the lower position when the pressure differential drops below a safe pressure differential.
    Type: Application
    Filed: March 15, 2004
    Publication date: May 19, 2005
    Inventors: Abderrafi Ougouag, Richard Schultz, William Terry
  • Patent number: 6861864
    Abstract: A test vehicle a system and method for evaluating an interconnect module manufacturing process while dynamically testing performance with high-speed operational frequencies is disclosed. An interconnect module designed at many of the manufacturing process limits offers complete and fast failure analysis so that manufacturing defects can be quickly located and the process improved. Failure analysis, particularly on 90 nm technologies and beyond is becoming extremely difficult. At-speed testing is also becoming very important to the yield and reliability of products. This invention incorporates a self-timed speed circuit that can detect subtle resistive faults and also show the exact location in the array where the speed fault occurred based on test program datalogs from scan flip flops.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: March 1, 2005
    Assignee: LSI Logic Corporation
    Inventor: Richard Schultz
  • Publication number: 20050041454
    Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a manufacturing process. The cells can be configured to operate as ring oscillators increasing the effective circuit frequency of the test module allowing higher frequency circuit testing, and shortening the time it takes to perform life cycle testing. Visibly marking cells, combined with electrically isolating error prone circuit segments makes, identifying defects much more efficient. The accessibility of many testing methods allows quick location of root cause failures, which allows improvements to be made to the manufacturing process.
    Type: Application
    Filed: August 18, 2004
    Publication date: February 24, 2005
    Inventors: Richard Schultz, Michael Schmidt
  • Patent number: 6851098
    Abstract: Static timing analysis results from multiple corner cases are combined to create a differential results table that may be used to identify components that are a high risk for failure. These results may be combined with a schematic analysis tool that finds overlapping logic cones for specific nodes of a circuit such as a failing output pin. These tools are specifically adapted to assist an engineer in the design and debugging of complex circuits, such as integrated circuits.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: February 1, 2005
    Assignee: LSI Logic Corporation
    Inventor: Richard Schultz
  • Publication number: 20050015651
    Abstract: A test vehicle a system and method for evaluating an interconnect module manufacturing process while dynamically testing performance with high-speed operational frequencies is disclosed. The test vehicle incorporates a self-timed or gated speed circuit that can detect subtle resistive faults and also show the exact location in the array where the speed fault occurred based on test program data logs from scan flip flops. One embodiment incorporates a gated clock in the gated speed circuit producing gated data that delivers greater statistical properties with respect to Integrated Circuit Direct Drain Quiescent Current (IDDQ) testing.
    Type: Application
    Filed: July 27, 2004
    Publication date: January 20, 2005
    Inventors: Richard Schultz, Derryl Allman, Jan Fure
  • Publication number: 20040207406
    Abstract: A test vehicle a system and method for evaluating an interconnect module manufacturing process while dynamically testing performance with high-speed operational frequencies is disclosed. An interconnect module designed at many of the manufacturing process limits offers complete and fast failure analysis so that manufacturing defects can be quickly located and the process improved. Failure analysis, particularly on 90 nm technologies and beyond is becoming extremely difficult. At-speed testing is also becoming very important to the yield and reliability of products. This invention incorporates a self-timed speed circuit that can detect subtle resistive faults and also show the exact location in the array where the speed fault occurred based on test program datalogs from scan flip flops.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 21, 2004
    Inventor: Richard Schultz
  • Patent number: 6781151
    Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits comprises a staircase of vias and traces arranged for maximum test coverage. The staircase may be combined with several functional cells to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of manufacturing process. The accessibility of many testing methods allows an engineer to quickly find root cause failures and thus make improvements to the manufacturing process.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: August 24, 2004
    Assignee: LSI Logic Corporation
    Inventors: Richard Schultz, Steve Howard
  • Publication number: 20040102915
    Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits comprises a staircase of vias and traces arranged for maximum test coverage. The staircase may be combined with several functional cells to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of manufacturing process. The accessibility of many testing methods allows an engineer to quickly find root cause failures and thus make improvements to the manufacturing process.
    Type: Application
    Filed: November 27, 2002
    Publication date: May 27, 2004
    Inventors: Richard Schultz, Steve Howard
  • Patent number: D511421
    Type: Grant
    Filed: January 21, 2001
    Date of Patent: November 15, 2005
    Inventor: Moses Richard Schultz