Patents by Inventor Rintaro Koda

Rintaro Koda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8218596
    Abstract: A Vertical Cavity Surface Emitting Laser capable of decreasing the lowering of the yield due to displacement and separation of a pedestal without enormous increase of the threshold value and more difficult manufacturing process is provided. A base of a mesa spreads over the top face of a lower DBR layer. The base is a non-flat face in which end faces of a plurality of layers are exposed. The non-flat face is generated due to etching unevenness in forming the mesa, and is in a state of a step in which end faces of a low-refractive index layer and a high-refractive index layer included in the lower DBR layer are alternatively exposed. At least one of the layers exposed in the non-flat face in the plurality of low-refractive index layers included in the lower DBR layer is an oxidation inhibition layer.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: July 10, 2012
    Assignee: Sony Corporation
    Inventors: Tomoyuki Oki, Rintaro Koda, Naoki Jogan, Yuji Masui, Takahiro Arakida
  • Publication number: 20120147917
    Abstract: A laser diode device includes a laminated structure in which a first compound semiconductor layer, a third compound semiconductor layer that has a light emitting region and a saturable absorption region, and a second compound semiconductor layer are sequentially layered, a second electrode, and a first electrode. The laminated structure has ridge stripe structure. The second electrode is separated into a first section to obtain forward bias state by applying a direct current to the first electrode through the light emitting region and a second section to add electric field to the saturable absorption region by an isolation trench. When minimum width of the ridge stripe structure is WMIN, and width of the ridge stripe structure of the second section of the second electrode in an interface between the second section of the second electrode and the isolation trench is W2, 1<W2/WMIN is satisfied.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 14, 2012
    Applicants: Tohoku University, Sony Corporation
    Inventors: Tomoyuki Oki, Hideki Watanabe, Rintaro Koda, Masaru Kuramoto, Hiroyuki Yokoyama
  • Patent number: 8183074
    Abstract: A method for manufacturing a light emitting element includes the steps of (A) forming sequentially a first compound semiconductor layer having a first conduction type, an active layer, and a second compound semiconductor layer having a second conduction type on a substrate, (B) forming a plurality of point-like hole portions in a thickness direction in at least a region of the second compound semiconductor layer located outside a region to be provided with a current confinement region, and (C) forming an insulating region by subjecting a part of the second compound semiconductor layer to an insulation treatment from side walls of the hole portions so as to produce the current confinement region surrounded by the insulating region in the second compound semiconductor layer.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: May 22, 2012
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Rintaro Koda, Tomoyuki Oki
  • Publication number: 20120034720
    Abstract: A Vertical Cavity Surface Emitting Laser capable of decreasing the lowering of the yield due to displacement and separation of a pedestal without enormous increase of the threshold value and more difficult manufacturing process is provided. A base of a mesa spreads over the top face of a lower DBR layer. The base is a non-flat face in which end faces of a plurality of layers are exposed. The non-flat face is generated due to etching unevenness in forming the mesa, and is in a state of a step in which end faces of a low-refractive index layer and a high-refractive index layer included in the lower DBR layer are alternatively exposed. At least one of the layers exposed in the non-flat face in the plurality of low-refractive index layers included in the lower DBR layer is an oxidation inhibition layer.
    Type: Application
    Filed: October 12, 2011
    Publication date: February 9, 2012
    Applicant: Sony Corporation
    Inventors: Tomoyuki Oki, Rintaro Koda, Naoki Jogan, Yuji Masui, Takahiro Arakida
  • Patent number: 8102890
    Abstract: A semiconductor light emitting device includes a first-conductivity-type first multilayer film reflecting mirror, and a second-conductivity-type second multilayer film reflecting mirror; a cavity layer; and a first conductive section, a second conductive section, and a third conductive section. The cavity layer has a stacked configuration including a first-conductivity-type or undoped first cladding layer, an undoped first active layer, a second-conductivity-type or undoped second cladding layer, a second-conductivity-type first contact layer, a first-conductivity-type second contact layer, a first-conductivity-type or undoped third cladding layer, an undoped second active layer, and a second-conductivity-type or undoped fourth cladding layer.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 24, 2012
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Rintaro Koda, Tomoyuki Oki, Naoki Jogan
  • Publication number: 20120009704
    Abstract: A vertical cavity surface emitting laser capable of reducing parasitic capacitance while suppressing power consumption, and a method of manufacturing thereof are provided. The vertical cavity surface emitting laser includes a columnar mesa including, on a substrate, a first multilayer reflector, an active layer, and a second multilayer reflector in order from the substrate side, and also including a current narrowing layer. The columnar portion of the mesa including the active layer and the current narrowing layer is formed within a region opposed to the first multilayer reflector and a region opposed to the second multilayer reflector, and a cross section area of the columnar portion is smaller than a cross section area of the second multilayer reflector.
    Type: Application
    Filed: September 19, 2011
    Publication date: January 12, 2012
    Applicant: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Terukazu Naruse, Rintaro Koda, Naoki Jogan
  • Publication number: 20120002271
    Abstract: A semiconductor optical amplifier includes: a laminated structure sequentially including a first compound semiconductor layer composed of GaN compound semiconductor and having a first conductivity type, a third compound semiconductor layer having a light amplification region composed of GaN compound semiconductor, and a second compound semiconductor layer composed of GaN compound semiconductor and having a second conductivity type; a second electrode formed on the second compound semiconductor layer; and a first electrode electrically connected to the first compound semiconductor layer. The laminated structure has a ridge stripe structure. When widths of the ridge stripe structure in a light output end face and the ridge stripe structure in a light incident end face are respectively Wout, and Win, Wout>Win is satisfied. A carrier non-injection region is provided in an internal region of the laminated structure from the light output end face along an axis line of the semiconductor optical amplifier.
    Type: Application
    Filed: June 23, 2011
    Publication date: January 5, 2012
    Applicants: Tohoku University, SONY CORPORATION
    Inventors: Masaru Kuramoto, Masao Ikeda, Rintaro Koda, Tomoyuki Oki, Hideki Watanabe, Takao Miyajima, Hiroyuki Yokoyama
  • Publication number: 20120002696
    Abstract: Provided is an alignment method of a semiconductor optical amplifier with which optimization of coupling efficiency between incident laser light and light waveguide of the semiconductor optical amplifier is enabled without depending on an external monitoring device. The alignment method of a semiconductor optical amplifier is a method that optically amplifies laser light from a laser light source and outputs the optically amplified laser light, which adjusts relative position of the semiconductor optical amplifier with respect to the laser light entering into the semiconductor optical amplifier by flowing a given value of current to the semiconductor optical amplifier while entering the laser light from the laser light source to the semiconductor optical amplifier so that a voltage applied to the semiconductor optical amplifier becomes the maximum.
    Type: Application
    Filed: June 17, 2011
    Publication date: January 5, 2012
    Applicants: TOHOKU UNIVERSITY, SONY CORPORATION
    Inventors: Tomoyuki Oki, Rintaro Koda, Masaru Kuramoto, Takao Miyajima, Hiroyuki Yokoyama
  • Patent number: 8085827
    Abstract: A Vertical Cavity Surface Emitting Laser capable of decreasing the lowering of the yield due to displacement and separation of a pedestal without enormous increase of the threshold value and more difficult manufacturing process is provided. A base of a mesa spreads over the top face of a lower DBR layer. The base is a non-flat face in which end faces of a plurality of layers are exposed. The non-flat face is generated due to etching unevenness in forming the mesa, and is in a state of a step in which end faces of a low-refractive index layer and a high-refractive index layer included in the lower DBR layer are alternatively exposed. At least one of the layers exposed in the non-flat face in the plurality of low-refractive index layers included in the lower DBR layer is an oxidation inhibition layer.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: December 27, 2011
    Assignee: Sony Corporation
    Inventors: Tomoyuki Oki, Rintaro Koda, Naoki Jogan, Yuji Masui, Takahiro Arakida
  • Publication number: 20110294236
    Abstract: A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value.
    Type: Application
    Filed: August 8, 2011
    Publication date: December 1, 2011
    Applicant: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Kayoko Kikuchi, Rintaro Koda, Norihiko Yamaguchi
  • Patent number: 8040934
    Abstract: A vertical cavity surface emitting laser capable of reducing parasitic capacitance while suppressing power consumption, and a method of manufacturing thereof are provided. The vertical cavity surface emitting laser includes a columnar mesa including, on a substrate, a first multilayer reflector, an active layer, and a second multilayer reflector in order from the substrate side, and also including a current narrowing layer. The columnar portion of the mesa including the active layer and the current narrowing layer is formed within a region opposed to the first multilayer reflector and a region opposed to the second multilayer reflector, and a cross section area of the columnar portion is smaller than a cross section area of the second multilayer reflector.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: October 18, 2011
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Terukazu Naruse, Rintaro Koda, Naoki Jogan
  • Patent number: 8035187
    Abstract: The present invention provides a semiconductor light receiving element capable of reducing capacity while minimizing increase in travel time of carriers. The semiconductor light receiving element includes a semiconductor stacked structure including a first conductivity type layer, a light absorbing layer, and a second conductivity type layer having a light incidence plane in order. The semiconductor light receiving element has an oxidation layer including a non-oxidation region and an oxidation region in a stacking in-plane direction in the light absorbing layer or between the first conductivity type layer and the light absorbing layer.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: October 11, 2011
    Assignee: Sony Corporation
    Inventors: Yoshinori Yamauchi, Takahiro Arakida, Rintaro Koda, Norihiko Yamaguchi, Yuji Masui, Tomoyuki Oki
  • Patent number: 8022424
    Abstract: A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: September 20, 2011
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Kayoko Kikuchi, Rintaro Koda, Norihiko Yamaguchi
  • Publication number: 20110176570
    Abstract: A semiconductor light emitting device includes a first-conductivity-type first multilayer film reflecting mirror, and a second-conductivity-type second multilayer film reflecting mirror; a cavity layer; and a first conductive section, a second conductive section, and a third conductive section. The cavity layer has a stacked configuration including a first-conductivity-type or undoped first cladding layer, an undoped first active layer, a second-conductivity-type or undoped second cladding layer, a second-conductivity-type first contact layer, a first-conductivity-type second contact layer, a first-conductivity-type or undoped third cladding layer, an undoped second active layer, and a second-conductivity-type or undoped fourth cladding layer.
    Type: Application
    Filed: March 21, 2011
    Publication date: July 21, 2011
    Applicant: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Rintaro Koda, Tomoyuki Oki, Naoki Jogan
  • Patent number: 7965750
    Abstract: A semiconductor light emitting device includes a first-conductivity-type first multilayer film reflecting mirror, and a second-conductivity-type second multilayer film reflecting mirror; a cavity layer; and a first conductive section, a second conductive section, and a third conductive section. The cavity layer has a stacked configuration including a first-conductivity-type or undoped first cladding layer, an undoped first active layer, a second-conductivity-type or undoped second cladding layer, a second-conductivity-type first contact layer, a first-conductivity-type second contact layer, a first-conductivity-type or undoped third cladding layer, an undoped second active layer, and a second-conductivity-type or undoped fourth cladding layer.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: June 21, 2011
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Rintaro Koda, Tomoyuki Oki, Naoki Jogan
  • Publication number: 20110122910
    Abstract: The present invention provides a semiconductor device realizing reduced occurrence of a defect such as a crack at the time of adhering elements to each other. The semiconductor device includes a first element and a second element adhered to each other. At least one of the first and second elements has a pressure relaxation layer on the side facing the other of the first and second elements, and the pressure relaxation layer includes a semiconductor part having a projection/recess part including a projection projected toward the other element, and a resin part filled in a recess in the projection/recess part.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 26, 2011
    Applicant: Sony Corporation
    Inventors: Rintaro Koda, Takahiro Arakida, Yuji Masui, Tomoyuki Oki
  • Publication number: 20110103419
    Abstract: The present invention provides an optical device capable of suppressing a drive current and an optical output to be varied with a passage of the time. The optical device includes: an optical element including a first end face and a second end face, and emitting light having a wavelength from 300 nm to 600 nm both inclusive at least from the second end face in the first end face and the second end face; a pedestal including a supporting substrate supporting the optical element, and a connecting terminal electrically connected to the optical element; and a sealing section including a light transmitting window in each of a portion facing the first end face and a portion facing the second end face, and sealing the optical element.
    Type: Application
    Filed: October 22, 2010
    Publication date: May 5, 2011
    Applicants: TOHOKU UNIVERSITY, Sony Corporation
    Inventors: Rintaro Koda, Takao Miyajima, Hideki Watanabe, Hiroyuki Yokoyama, Tomoyuki Oki, Masaru Kuramoto
  • Publication number: 20110103420
    Abstract: A laser diode with which high density crystal defect and surface roughness are able to be inhibited from being generated is provided. The laser diode includes a laminated body including an active layer and a current narrowing layer on a substrate. The substrate is an inclined substrate having an off-angle larger than 0 degrees in the direction of [1-100] from (0001) C plane.
    Type: Application
    Filed: September 30, 2010
    Publication date: May 5, 2011
    Applicant: Sony Corporation
    Inventors: Rintaro Koda, Yusuke Nakayama
  • Publication number: 20110064109
    Abstract: A laser diode with which separation of a current narrowing layer is able to be prevented is provided. The laser diode includes a mesa that has a first multilayer film reflector, an active layer, and a second multilayer film reflector in this order, and has a current narrowing layer for narrowing a current injected into the active layer and a buffer layer adjacent to the current narrowing layer. The current narrowing layer is formed by oxidizing a first oxidized layer containing Al. The buffer layer is formed by oxidizing a second oxidized layer whose material and a thickness are selected so that an oxidation rate is higher than that of the first multilayer film reflector and the second multilayer film reflector and is lower than that of the first oxidized layer. A thickness of the buffer layer is 10 nm or more.
    Type: Application
    Filed: August 23, 2010
    Publication date: March 17, 2011
    Applicant: Sony Corporation
    Inventors: Yuji Masui, Rintaro Koda, Tomoyuki Oki, Takahiro Arakida, Naoki Jogan, Yoshinori Yamauchi
  • Patent number: 7884386
    Abstract: A semiconductor light-emitting device includes a semiconductor light-emitting element including a first multilayer reflector, an active layer having a light-emitting region, and a second multilayer reflector in the stated order; a semiconductor light-detecting element disposed opposite the first multilayer reflector in relation to the semiconductor light-emitting element and including a light-absorbing layer configured to absorb light emitted from the light-emitting region; a transparent substrate disposed between the semiconductor light-emitting element and the semiconductor light-detecting element; a first metal layer having a first opening in a region including a region opposite the light-emitting region and bonding the semiconductor light-emitting element and the substrate; and a second metal layer having a second opening in a region including a region opposite the light-emitting region and bonding the semiconductor light-detecting element and the substrate.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: February 8, 2011
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Rintaro Koda, Osamu Maeda, Takahiro Arakida, Terukazu Naruse, Naoki Jogan