Patents by Inventor Rishabh

Rishabh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10999244
    Abstract: The techniques described herein enable a private connectivity solution between a virtual network of a service consumer and a virtual network of a service provider in a cloud-based platform. The techniques map a service (e.g., one or more workloads or containers) executing in the virtual network of the service provider into the virtual network of the service consumer. The mapping uses network address translation (NAT) that is performed by the cloud-based infrastructure. As a result of the techniques described herein, a public Internet Protocol (IP) address does not need to be used to establish a connection thereby alleviating privacy and/or security concerns for the virtual networks of the service provider and/or the service consumer that are hosted by the cloud-based platform.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: May 4, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sumeet Mittal, Abhishek Shukla, Rishabh Tewari, Qiming Chen, Harish Kumar Chandrappa, Pranjal Shrivastava, Anitha Adusumilli, Parag Sharma, Abhishek Ellore Sreenath
  • Patent number: 10996972
    Abstract: A virtual network interface controller (NIC) associated with a virtual machine in a cloud computing network is configured to support one or more network containers that encapsulate networking configuration data and policies that are applicable to a specific discrete computing workload to thereby enable the virtual machine to simultaneously belong to multiple virtual networks using the single NIC. The network containers supported by the NIC can be associated with a single tenant to enable additional flexibility such quickly switching between virtual networks and support pre-provisioning of additional computing resources with associated networking policies for rapid deployment. The network containers can also be respectively associated with different tenants so that the single NIC can support multi-tenant services on the same virtual machine.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 4, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Abhishek Shukla, Abhishek Ellore Sreenath, Neha Aggarwal, Naveen Prabhat, Nisheeth Srivastava, Xinyan Zan, Ashish Bhargava, Parag Sharma, Rishabh Tewari
  • Patent number: 10997608
    Abstract: A system and method for generating an insult rate and reconfiguring an automated decisioning workflow includes configuring a testing group based on sampling from online events having an adverse disposal decision computed by an automated decisioning workflow computer that is configured with machine learning-based threat score thresholds that, if satisfied, causes a computation of a disallow decision or a block decision for a given online event; evaluating a performance and collecting performance data of distinct members of the testing group over a testing period; computing an insult rate for the testing group based on the performance data; computing an insult rate equilibrium for the automated decisioning workflow computer based on the performance data; evaluating the insult rate against the insult rate equilibrium; and reconfiguring adverse decisioning thresholds based on the evaluation of the insult rate of the testing group against the insult rate equilibrium for the automated decisioning workflow computer.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: May 4, 2021
    Assignee: Sift Science, Inc.
    Inventors: Rajiv Veeraraghavan, Pradhan Bagur Umesh, Rishabh Kothari, Abbey Chaver
  • Patent number: 10991696
    Abstract: An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Patrick Theofanis, Cory E. Weber, Stephen M. Cea, Rishabh Mehandru
  • Patent number: 10983853
    Abstract: Provided are methods and systems for automatically generating input grammars for grammar-based fuzzing by utilizing machine-learning techniques and sample inputs. Neural-network-based statistical learning techniques are used for the automatic generation of input grammars. Recurrent neural networks are used for learning a statistical input model that is also generative in that the model is used to generate new inputs based on the probability distribution of the learnt model.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: April 20, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Patrice Godefroid, Rishabh Singh, Hila Peleg
  • Publication number: 20210111115
    Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 15, 2021
    Applicant: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Mark T. Bohr, Tahir Ghani, Rishabh Mehandru
  • Patent number: 10978590
    Abstract: Methods and apparatus to remove epitaxial defects in semiconductors are disclosed. A disclosed example multilayered die structure includes a fin having a first material, where the fin is epitaxially grown from a first substrate layer having a second material, and where a defect portion of the fin is etched or polished. The disclosed example multilayered die structure also includes a second substrate layer having an opening through which the fin extends.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Patrick Morrow, Patrick H. Keys
  • Patent number: 10979871
    Abstract: A tracking device is described. The tracking device receives, from a management server, configuration parameters including a first data transmission rate and a second data transmission rate. The tracking device automatically enters into an active mode of the tracking device. When operating in an active mode, the tracking device, is operative to transmit, in response to determining based on first motion sensor measurements that the asset is stationary, first location data at the first data transmission rate. In response to determining, based on second motion sensor measurements and motion definition parameters, that the asset is mobile, the tracking device is operative to transmit, second location data of the asset at the second data transmission rate.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 13, 2021
    Assignee: Samsara Networks Inc.
    Inventors: Hadi Hajimiri, Rishabh Gupta, Ye-Sheng Kuo, Kenneth Lee, Siri Amrit Ramos, Justin Tingao Xiao, Pete Nicholas Chulick, Gautam Ravi Ramaswamy
  • Patent number: 10969429
    Abstract: The present disclosure relates to a system and method for debugging in fault simulation associated with an electronic design. Embodiments may include receiving, using at least one processor, an electronic design and performing concurrent fault simulation on a fault to be analyzed associated with the electronic circuit design, wherein the fault has a fault propagation path associated therewith. Embodiments may also include identifying a trace of one or more signals of interest that are in the fault propagation path and generating a faulty database and a good database associated with the one or more signals of interest that are in the fault propagation path. Embodiments may further include identifying one or more differences between the faulty database and the good database.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: April 6, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Manoj Kumar, Rishabh Gupta, Inderpreet Singh Baweja
  • Publication number: 20210091080
    Abstract: An integrated circuit structure comprises a lower device layer that includes a first structure comprising a plurality of PMOS transistors. An upper device layer is formed on the lower device layer, wherein the upper device layer includes a second structure comprising a plurality of NMOS thin-film transistors (TFT).
    Type: Application
    Filed: March 28, 2018
    Publication date: March 25, 2021
    Inventors: Gilbert DEWEY, Ravi PILLARISETTY, Abhishek A. SHARMA, Aaron D. LILAK, Willy RACHMADY, Rishabh MEHANDRU, Kimin JUN, Anh PHAN, Hui Jae YOO, Patrick MORROW, Cheng-Ying HUANG
  • Patent number: 10956169
    Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: March 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Yogesh Vikram Marathe, Kedar Satish Chitnis, Rishabh Garg
  • Patent number: 10956219
    Abstract: Systems and methods may use models to generate predictions of specific access rights for users. Further, systems and methods may generate the predictions in an environment in which the availability of the specific access rights change frequently. The access rights, predicted using embodiments described herein, may be both available and associated with user affinities. An interface associated with the primary load management system may be configured to display the predicted access rights for a user operating a user device.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: March 23, 2021
    Assignee: Live Nation Entertainment, Inc.
    Inventors: Ish Rishabh, Mark Roden, Chris Smith, Spencer Brown, Scott Kline, Krisha Zagura
  • Publication number: 20210083117
    Abstract: Techniques and mechanisms to impose stress on a transistor which includes a channel region and a source or drain region each in a fin structure. In an embodiment, a gate structure of the transistor extends over the fin structure, wherein a first spacer portion is at a sidewall of the gate structure and a second spacer portion adjoins the first spacer portion. Either or both of two features are present at or under respective bottom edges of the spacer portions. One of the features includes a line of discontinuity on the fin structure. The other feature includes a concentration of a dopant in the second spacer portion being greater than a concentration of the dopant in the source or drain region. In another embodiment, the fin structure is disposed on a buffer layer, wherein stress on the channel region is imposed at least in part with the buffer layer.
    Type: Application
    Filed: September 29, 2017
    Publication date: March 18, 2021
    Applicant: INTEL CORPORATION
    Inventors: Rishabh Mehandru, Stephen M. Cea, Tahir Ghani, Anand S. Murthy
  • Patent number: 10950130
    Abstract: Among other things, equipment is located at an intersection of a transportation network. The equipment includes an input to receive data from a sensor oriented to monitor ground transportation entities at or near the intersection. A wireless communication device sends to a device of one of the ground transportation entities, a warning about a dangerous situation at or near the intersection, there is a processor and a storage for instructions executable by the processor to perform actions including the following. A machine learning model is stored that can predict behavior of ground transportation entities at or near the intersection at a current time. The machine learning model is based on training data about previous motion and related behavior of ground transportation entities at or near the intersection.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: March 16, 2021
    Inventors: Georges Aoude, Amer Abufadel, Karl Jeanbart, Rishabh Choudhary, Ankit Sharma
  • Publication number: 20210075889
    Abstract: An enterprise application executed on a user device is configured to perform steps of providing functionality for a user device while operating in background on the user device; determining an issue with the functionality of the enterprise application; presenting a user of the user device a list of a plurality of issue types for selection thereof; receiving a selection from the user of an issue type for the issue; and collecting data from the user device based on the selected issue type. The steps can further include transmitting the collected data to a back end server for troubleshooting of the issue.
    Type: Application
    Filed: October 21, 2019
    Publication date: March 11, 2021
    Inventors: Rohit Goyal, Rishabh Gupta
  • Publication number: 20210074704
    Abstract: An integrated circuit structure includes a first portion of a bottom semiconductor fin extending horizontally in a length direction and vertically in a height direction, a second portion of the bottom semiconductor fin extending horizontally in the length direction and vertically in the height direction, a top semiconductor fin extending horizontally in the length direction and vertically in the height direction, and an insulator region extending horizontally in the length direction to electrically insulate the first portion of the bottom semiconductor fin from the second portion of the bottom semiconductor fin. The insulator region further extends vertically in the height direction in vertical alignment with the top semiconductor fin. The insulator region includes at least one of an insulator material and an airgap. In an embodiment, the top semiconductor fin is associated with a transistor, and the insulator region is in vertical alignment with a gate electrode of the transistor.
    Type: Application
    Filed: January 10, 2018
    Publication date: March 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Aaron D. Lilak, Gilbert Dewey, Willy Rachmady, Patrick Morrow, Rishabh Mehandru
  • Publication number: 20210075811
    Abstract: Systems and methods include providing functionality for a user device while operating in background on the user device; responsive to a user request, starting collection of packets intercepted by the enterprise application; storing the collected packets on the user device; receiving a selection from the user of an issue type of a plurality of issue types for an issue; and providing the issue type and the collected packets for debugging of the issue type. The systems and methods can further include transmitting the collected data and the collected packets to a back end server for troubleshooting of the issue.
    Type: Application
    Filed: August 13, 2020
    Publication date: March 11, 2021
    Inventors: Rishabh Gupta, Rohit Goyal
  • Publication number: 20210075068
    Abstract: Methods and systems for detecting and compensating for expansion of rechargeable batteries over time. An expansion detector may be coupled to or positioned proximate a rechargeable battery to monitor for expansion thereof. After expansion exceeding a selected threshold is detected, the expansion detector may report the expansion to an associated processing unit. The processing unit may undertake to arrest further rechargeable battery expansion by modifying or changing one or more characteristics of charging and/or discharging circuitry coupled to the rechargeable battery. For example, the processing unit may charge the rechargeable battery at a lower rate or with reduced voltage after detecting expansion.
    Type: Application
    Filed: November 16, 2020
    Publication date: March 11, 2021
    Inventors: Daniel W. Jarvis, David M. DeMuro, Hongli Dai, Julian Malinski, Julien Marcil, Meng Chi Lee, Richard Hung Minh Dinh, Rishabh Bhargava, Steven D. Sterz, Richard M. Mank, Soundararajan Manthiri, Vijayasekaran Boovaragavan
  • Patent number: 10934070
    Abstract: A film for packaging a product that has a pharmaceutical active agent includes a product-contacting sealing layer. The product contacting layer includes at least 90 wt. % of an ethylene norbornene copolymer having a glass transition temperature in a range from 50° C. to 110° C. The pharmaceutical active agent comprises a Hansen Solubility Parameter for the product-contacting sealing layer of 0.5 or greater.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: March 2, 2021
    Assignee: Bemis Company, Inc.
    Inventors: Jennifer L. Riis, Yuan Liu, Lyndsey A. McMillan, Christopher L. Osborn, Rishabh Jain
  • Patent number: 10938660
    Abstract: An example method includes identifying, based on a received indication, at least a first network device that is to be placed in the maintenance mode, determining device information for the first network device, sending, to the first network device, first configuration information included in the device information to cause the first network device to switch into a maintenance mode and enable diversion of network traffic from the first network device to a second network device, responsive to verifying that the first network device has diverted the traffic, initiating maintenance procedures on the first network device while the first network device is in the maintenance mode, and sending, to the first network device, second configuration information included in the device information to cause the first network device to switch out of the maintenance mode and enable reversion of network traffic from the second device to the first network device.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: March 2, 2021
    Assignee: Juniper Networks, Inc.
    Inventors: Sukhdev S. Kapur, Ashok Ganesan, Jacopo Pianigiani, Michal Styszynski, Atul S Moghe, Joseph Williams, Sahana Sekhar Palagrahara Chandrashekar, Tong Jiang, Rishabh Ramakant Tulsian, Manish Krishnan, Soumil Ramesh Kulkarni, Vinod Nair, Jeba Paulaiyan