Patents by Inventor Robert Burke

Robert Burke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090249067
    Abstract: A system and method for pre-placing content from a provider on an end user storage device is described. The system includes a device connected to an end user network and a public network and used to interface with one or more digital keys, where each digital key is able to control one or more identity associations. A storage device attached to the end user network and is able to receive content from the provider using the identity association with the provider. The content is encrypted on the storage device using a keys established by the provider, such that the end user can only decrypt and access the content by agreeing to terms established by the provider using the digital key and identity association with the provider.
    Type: Application
    Filed: March 25, 2008
    Publication date: October 1, 2009
    Applicant: Contineo Systems
    Inventors: Milton Lie, Brian Forbes, Robert Burke, Ernest Oakes
  • Publication number: 20090198996
    Abstract: A system and method for providing a identity association between a subscriber in a private network and a provider over a public network is described. The system and method include a subscriber security gateway in the private network, the subscriber security gateway providing policy enforcement and signaling between the private network and the provider over the public network and at least one digital key associated with the provider and readable by the subscriber security gateway and operable to provide a identity association with the provider.
    Type: Application
    Filed: February 4, 2008
    Publication date: August 6, 2009
    Applicant: Contineo Systems
    Inventors: Milton Lie, Brian Forbes, Robert Burke
  • Patent number: 7542655
    Abstract: A method, apparatus, system, and signal-bearing medium that in an embodiment save presented clips of a program and delete unpresented clips of the program. Meta-data associated with the program or embedded in the program to delineate the presented clips. The meta-data are created in response to commands that cause or end the presentation of the program, such as play, slow motion, skip, fast forward, or rewind commands.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: June 2, 2009
    Assignee: International Business Machines Corporation
    Inventors: Michael Robert Burke, Frederick Allyn Kulack, Kevin Glynn Paterson
  • Patent number: 7470576
    Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: December 30, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Michael P. Violette, Robert Burke
  • Publication number: 20080311719
    Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
    Type: Application
    Filed: August 13, 2008
    Publication date: December 18, 2008
    Inventors: Sanh D. Tang, Michael P. Violette, Robert Burke
  • Patent number: 7465616
    Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: December 16, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Michael P. Violette, Robert Burke
  • Publication number: 20080281003
    Abstract: A process for preparing functionalised microporous polymers (which are also known as micro-cellular polymers or polyHIPE polymers (PHPs)) using intensified internal heating (for example by microwave irradiation).
    Type: Application
    Filed: April 13, 2006
    Publication date: November 13, 2008
    Applicant: University of Newcastle Upon Tyne School Of Chemical Engineering and Advanced Materials
    Inventors: Galip Akay, Zainura Zainon Noor, Omer Faruk Calkan, Teresa Manguangua Ndlovu, David Robert Burke
  • Publication number: 20080255681
    Abstract: Methods and apparatus to manage process plant alarms are disclosed. An example disclosed method comprises performing a first data structure query to obtain an alarm state for a process plant alarm based on a process plant operating state, and configuring handling of the process plant alarm based on the obtained alarm state.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 16, 2008
    Inventors: Cindy Alsup Scott, Robert Burke Havekost, Michael George Ott
  • Publication number: 20080189441
    Abstract: Methods and apparatus to configure process control system inputs and outputs are disclosed. A disclosed example method comprises obtaining a tag of a process control device from the input/output device, and associating the process control device with a process control module based on the obtained tag.
    Type: Application
    Filed: February 2, 2007
    Publication date: August 7, 2008
    Inventors: Larry Oscar Jundt, Kent Allan Burr, Gary Keith Law, William George Irwin, Marty James Lewis, Michael George Ott, Robert Burke Havekost
  • Publication number: 20080169336
    Abstract: A welding apparatus is disclosed. The welding apparatus includes a torch body comprising at least one core, a plurality of contact tips extending in a direction from the at least one core, and a plurality of gas supply tubes disposed proximate the plurality of contact tips, the plurality of gas supply tubes extending in a substantially similar direction as the plurality of contact tips.
    Type: Application
    Filed: January 11, 2007
    Publication date: July 17, 2008
    Inventors: Lyle B. Spiegel, Edward Kenneth Ellis, William Harold Childs, Peter Robert Burke
  • Publication number: 20080084972
    Abstract: An apparatus, program product and method that generate a user profile and verify the authorship of a second message against the user profile. As such, messages inconsistent with the user profile, which may be indicative of authorship by another user, may be detected primarily from one side of a communication, generally resulting in safer instant messaging and/or emailing. Additionally, reauthentication and/or blocking capabilities may be utilized to handle messages inconsistent with the user profile.
    Type: Application
    Filed: September 27, 2006
    Publication date: April 10, 2008
    Inventors: Michael Robert Burke, Zachary Adam Garbow, Kevin Glynn Paterson
  • Publication number: 20070224753
    Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
    Type: Application
    Filed: June 1, 2007
    Publication date: September 27, 2007
    Inventors: Sanh Tang, Robert Burke, Anand Srinivasan
  • Publication number: 20070151938
    Abstract: A display rack for rounded articles generally includes a product track with a pusher block slidably mounted thereon. The pusher block is biased toward a front portion of the display rack, and the side walls of the display rack are configured to support a circular or elliptical product. Additionally, the display rack can be provided with front and/or rear removable panel carriers configured to removably receive front and rear panels.
    Type: Application
    Filed: June 20, 2006
    Publication date: July 5, 2007
    Inventor: Robert Burke
  • Publication number: 20070102753
    Abstract: Various embodiments include a substrate having including a first doped region and a second doped region located on a first side of the substrate, and a third doped region and a fourth doped region located on a second side of the substrate, an insulation layer overlying the substrate, a gate layer overlying the insulation layer, a barrier layer overlying the gate layer, and an electrode layer overlying the barrier layer. The first and third doped regions may be located on a first side of the gate layer. The second and fourth doped regions may be located on a second side of the gate layer. The first and third doped regions may be source and drain regions of a first transistor. The second and fourth doped regions may be source and drain regions of a second transistor. The gate layer may include a gate segment to couple to a third transistor. Other embodiments are disclosed.
    Type: Application
    Filed: December 28, 2006
    Publication date: May 10, 2007
    Inventors: Sanh Tang, Chih-Chen Cho, Robert Burke, Anuradha Iyengar, Eugene Gifford
  • Publication number: 20070105323
    Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
    Type: Application
    Filed: December 20, 2006
    Publication date: May 10, 2007
    Inventors: Sanh Tang, Michael Violette, Robert Burke
  • Patent number: 7214613
    Abstract: A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of second conductivity type. The cross diffusion barrier layer includes a combination of silicon and nitrogen. The cross diffusion barrier layer adequately prevents cross diffusion between the first and second gate portions while causing no substantial increase in the resistance of the gate layer.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 8, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Chih-Chen Cho, Robert Burke, Anuradha Iyengar, Eugene R. Gifford
  • Publication number: 20070068427
    Abstract: A display rack for rounded articles generally includes a product track with a pusher block slidably mounted thereon. The pusher block is biased toward a front portion of the display rack, and the side walls of the display rack are configured to support a circular or elliptical product. Additionally, the display rack can be provided with front and/or rear removable panel carriers configured to removably receive front and rear panels.
    Type: Application
    Filed: November 28, 2006
    Publication date: March 29, 2007
    Inventor: Robert Burke
  • Publication number: 20070048943
    Abstract: A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.
    Type: Application
    Filed: May 23, 2006
    Publication date: March 1, 2007
    Inventors: Sanh Tang, Robert Burke, Anand Srinivasan
  • Patent number: 7166896
    Abstract: A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of second conductivity type. The cross diffusion barrier layer includes a combination of silicon and nitrogen. The cross diffusion barrier layer adequately prevents cross diffusion between the first and second gate portions while causing no substantial increase in the resistance of the gate layer.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: January 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Chih-Chen Cho, Robert Burke, Anuradha Iyengar, Eugene R. Gifford
  • Publication number: 20060276035
    Abstract: A contact structure and a method of forming thereof for semiconductor devices or assemblies are described. The method provides process steps to create a contact structure encompassed by a sacrificial contact medium having an opening therein that is lined with a conductive spacer liner that effectively prevents the contact structure from being damaged during removal of the surrounding sacrificial contact medium material. The sacrificial contact medium is then replaced with a non-boron doped dielectric material.
    Type: Application
    Filed: July 28, 2006
    Publication date: December 7, 2006
    Inventors: Grant Huglin, Robert Burke, Sanh Tang