Patents by Inventor Robert Hannon
Robert Hannon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8658535Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.Type: GrantFiled: May 9, 2013Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Paul S. Andry, Mukta G. Rarooq, Robert Hannon, Subramanian S. Iyer, Emily R. Kinser, Comelia K. Tsang, Richard P. Volant
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Patent number: 8629553Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.Type: GrantFiled: February 16, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Sampath Purushothaman, Roy R. Yu
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Patent number: 8546961Abstract: Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.Type: GrantFiled: January 10, 2011Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Troy L. Graves-Abe, Robert Hannon, Emily R. Kinser, William F. Landers, Kevin S. Petrarca, Richard P. Volant, Kevin R. Winstel
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Publication number: 20130244420Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.Type: ApplicationFiled: May 9, 2013Publication date: September 19, 2013Applicant: International Business Machines CorporationInventors: Paul S. Andry, Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Emily R. Kinser, Cornelia K. Tsang, Richard P. Volant
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Patent number: 8492869Abstract: A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.Type: GrantFiled: August 10, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu
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Patent number: 8492878Abstract: A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. A dielectric liner is formed by depositing a dielectric material on vertical portions of the diffusion barrier liner. A metallic conductive via structure is formed by subsequently filling the TSV trench. Horizontal portions of the diffusion barrier liner are removed. The diffusion barrier liner protects the semiconductor material of the substrate during the backside planarization by blocking residual metallic material originating from the metallic conductive via structure from entering into the semiconductor material of the substrate, thereby protecting the semiconductor devices within the substrate from metallic contamination.Type: GrantFiled: July 21, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Richard P. Volant
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Patent number: 8487425Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.Type: GrantFiled: June 23, 2011Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Paul S Andry, Mukta G Farooq, Robert Hannon, Subramanian S Iyer, Emily R Kinser, Cornelia K Tsang, Richard P Volant
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Patent number: 8455270Abstract: A process of forming three-dimensional (3D) die. A plurality of wafers are tested for die that pass (good die) or fail (bad die) predetermined test criteria. Two tested wafers are placed in proximity to each other. The wafers are aligned in such a manner so as to maximize the number of good die aligned between the two wafers. The two wafers are then bonded together and diced into individual stacks of bonded good die.Type: GrantFiled: September 17, 2009Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer
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Patent number: 8399336Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.Type: GrantFiled: August 19, 2008Date of Patent: March 19, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu
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Patent number: 8372725Abstract: Structures and methods are provided for forming pre-fabricated deep trench capacitors for SOI substrates. The method includes forming a trench in a substrate and forming a dielectric material in the trench. The method further includes depositing a conductive material over the dielectric material in the trench and forming an insulator layer over the conductive material and the substrate.Type: GrantFiled: February 23, 2010Date of Patent: February 12, 2013Assignee: International Business Machines CorporationInventors: Robert Hannon, Subramanian S. Iyer, Gerd Pfeiffer, Ravi M. Todi, Kevin R. Winstel
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Publication number: 20120326309Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.Type: ApplicationFiled: June 23, 2011Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: PAUL S ANDRY, Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Emily R. Kinser, Cornelia K. Tsang, Richard P. Volant
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Publication number: 20120309127Abstract: A computer readable medium is provided that is encoded with a program comprising instructions for performing a method for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer.Type: ApplicationFiled: August 10, 2012Publication date: December 6, 2012Applicant: International Business Machines CorporationInventors: Mukta G. FAROOQ, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu
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Publication number: 20120299200Abstract: A 3D integrated circuit structure is provided. The 3D integrated circuit structure includes an interface wafer including a first wiring layer, a first active circuitry layer including active circuitry, and a wafer including active circuitry. The first active circuitry layer is bonded face down to the interface wafer, and the wafer is bonded face down to the first active circuitry layer. The first active circuitry layer is lower-cost than the wafer.Type: ApplicationFiled: August 10, 2012Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. FAROOQ, Robert HANNON, Subramanian S. IYER, Steven J. KOESTER, Fei LIU, Sampath PURUSHOTHAMAN, Albert M. YOUNG, Roy R. YU
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Patent number: 8298914Abstract: A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method.Type: GrantFiled: August 19, 2008Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu
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Publication number: 20120181661Abstract: A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.Type: ApplicationFiled: March 23, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: ROGER A. BOOTH, JR., KANGGUO CHENG, ROBERT HANNON, RAVI M. TODI, GENG WANG
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Publication number: 20120175789Abstract: Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.Type: ApplicationFiled: January 10, 2011Publication date: July 12, 2012Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Troy L. Graves-Abe, Robert Hannon, Emily R. Kinser, William F. Landers, Kevin S. Patrarca, Richard P. Volant, Kevin R. Winstel
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Publication number: 20120153429Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.Type: ApplicationFiled: February 16, 2012Publication date: June 21, 2012Applicant: International Business Machines CorporationInventors: Mukta G. FAROOQ, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Sampath Purushothaman, Roy R. Yu
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Publication number: 20120149173Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a non-transitory computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.Type: ApplicationFiled: February 16, 2012Publication date: June 14, 2012Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Sampath Purushothaman, Roy R. Yu
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Patent number: 8129256Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.Type: GrantFiled: August 19, 2008Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Sampath Purushothaman, Roy R. Yu
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Publication number: 20120018851Abstract: A through-substrate via (TSV) structure that is immune to metal contamination due to a backside planarization process is provided. After forming a through-substrate via (TSV) trench, a diffusion barrier liner is conformally deposited on the sidewalls of the TSV trench. A dielectric liner is formed by depositing a dielectric material on vertical portions of the diffusion barrier liner. A metallic conductive via structure is formed by subsequently filling the TSV trench. Horizontal portions of the diffusion barrier liner are removed. The diffusion barrier liner protects the semiconductor material of the substrate during the backside planarization by blocking residual metallic material originating from the metallic conductive via structure from entering into the semiconductor material of the substrate, thereby protecting the semiconductor devices within the substrate from metallic contamination.Type: ApplicationFiled: July 21, 2010Publication date: January 26, 2012Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Richard P. Volant