Patents by Inventor Robert Hannon
Robert Hannon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures
Patent number: 8076756Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: GrantFiled: February 19, 2011Date of Patent: December 13, 2011Assignee: International Business Machines CorporationInventors: Michael W. Lane, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. W. Melville -
Patent number: 8022543Abstract: A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.Type: GrantFiled: March 25, 2008Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Emily R. Kinser, Ian D. Melville
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Publication number: 20110204524Abstract: Structures and methods are provided for forming pre-fabricated deep trench capacitors for SOI substrates. The method includes forming a trench in a substrate and forming a dielectric material in the trench. The method further includes depositing a conductive material over the dielectric material in the trench and forming an insulator layer over the conductive material and the substrate.Type: ApplicationFiled: February 23, 2010Publication date: August 25, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert HANNON, Subramanian S. IYER, Gerd PFEIFFER, Ravi M. TODI, Kevin R. WINSTEL
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STRUCTURE FOR INHIBITING BACK END OF LINE DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES
Publication number: 20110140245Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: ApplicationFiled: February 19, 2011Publication date: June 16, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MICHAEL W. LANE, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D.W. Melville -
Patent number: 7955955Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: GrantFiled: May 10, 2007Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Michael W. Lane, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. W. Melville
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Patent number: 7919356Abstract: A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.Type: GrantFiled: July 31, 2007Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Dae-Young Jung, Ian D. Melville
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Publication number: 20110065214Abstract: A process of forming three-dimensional (3D) die. A plurality of wafers are tested for die that pass (good die) or fail (bad die) predetermined test criteria. Two tested wafers are placed in proximity to each other. The wafers are aligned in such a manner so as to maximize the number of good die aligned between the two wafers. The two wafers are then bonded together and diced into individual stacks of bonded good die.Type: ApplicationFiled: September 17, 2009Publication date: March 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer
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Publication number: 20100314711Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer that includes active circuitry is provided, and a first portion of the first active circuitry layer wafer is removed such that a second portion of the first active circuitry layer wafer remains. Another wafer that includes active circuitry is provided, and the other wafer is bonded to the second portion of the first active circuitry layer wafer. The first active circuitry layer wafer is lower-cost than the other wafer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.Type: ApplicationFiled: August 19, 2008Publication date: December 16, 2010Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu, Sampath Purushothaman, Albert M. Young, Roy R. Yu
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Publication number: 20100264551Abstract: A method of implementing three-dimensional (3D) integration of multiple integrated circuit (IC) devices includes forming a first insulating layer over a first IC device; forming a second insulating layer over a second IC device; forming a 3D, bonded IC device by aligning and bonding the first insulating layer to the second insulating layer so as to define a bonding interface therebetween, defining a first set of vias within the 3D bonded IC device, the first set of vias landing on conductive pads located within the first IC device, and defining a second set of vias within the 3D bonded IC device, the second set of vias landing on conductive pads located within the second device, such that the second set of vias passes through the bonding interface; and filling the first and second sets of vias with a conductive material.Type: ApplicationFiled: April 20, 2009Publication date: October 21, 2010Applicant: International Business Machines CorporationInventors: MUKTA G. FAROOQ, ROBERT HANNON, SUBRAMANIAN S. IYER, EMILY R. KINSER
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Publication number: 20100200949Abstract: A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices.Type: ApplicationFiled: February 12, 2009Publication date: August 12, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Roger A. Booth, JR., Kangguo Cheng, Robert Hannon, Ravi M. Todi, Geng Wang
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Patent number: 7674690Abstract: A method divides a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the process exposes the chip to a heated ambient environment having a given pressure (e.g., less than one atmosphere). The environment comprises a chemical agent capable of bonding with the metallic substance. Additionally, wet chemical etch can be performed on the chip.Type: GrantFiled: July 15, 2008Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Da-Young Jung
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Publication number: 20100047964Abstract: A method is provided for fabricating a 3D integrated circuit structure. Provided are an interface wafer including a first wiring layer and through-silicon vias, and a first active circuitry layer wafer including active circuitry. The first active circuitry layer wafer is bonded to the interface wafer. Then, a first portion of the first active circuitry layer wafer is removed such that a second portion remains attached to the interface wafer. A stack structure including the interface wafer and the second portion of the first active circuitry layer wafer is bonded to a base wafer. Next, the interface wafer is thinned so as to form an interface layer, and metallizations coupled through the through-silicon vias in the interface layer to the first wiring layer are formed on the interface layer. Also provided is a tangible computer readable medium encoded with a program that comprises instructions for performing such a method.Type: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. FAROOQ, Robert HANNON, Subramanian S. IYER, Steven J. KOESTER, Fei LIU, Sampath PURUSHOTHAMAN, Albert M. YOUNG, Roy R. YU
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Publication number: 20100044826Abstract: A method is provided for fabricating a 3D integrated circuit structure. According to the method, a first active circuitry layer wafer is provided. The first active circuitry layer wafer comprises a P+ portion covered by a P? layer, and the P? layer includes active circuitry. The first active circuitry layer wafer is bonded face down to an interface wafer that includes a first wiring layer, and then the P+ portion of the first active circuitry layer wafer is selectively removed with respect to the P? layer of the first active circuitry layer wafer. Next, a wiring layer is fabricated on the backside of the P? layer. Also provided are a tangible computer readable medium encoded with a program for fabricating a 3D integrated circuit structure, and a 3D integrated circuit structure.Type: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. FAROOQ, Robert HANNON, Subramanian S. IYER, Steven J. KOESTER, Sampath PURUSHOTHAMAN, Roy R. YU
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Publication number: 20090243098Abstract: A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.Type: ApplicationFiled: March 25, 2008Publication date: October 1, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, Robert Hannon, Emily R. Kinser, Ian D. Melville
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Patent number: 7566637Abstract: Method of inhibiting metal diffusion arising from laser dicing is provided. The method includes dividing a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the method exposes the chip to a heated ambient environment having a given pressure (e.g., less than one atmosphere). The environment includes a chemical agent capable of bonding with the metallic substance. Additionally, wet chemical etch may be performed on the chip.Type: GrantFiled: December 13, 2007Date of Patent: July 28, 2009Assignee: International Business Machines CorporationInventors: Mukta G Farooq, Robert Hannon, Dae-Young Jung
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Publication number: 20090155983Abstract: Method of inhibiting metal diffusion arising from laser dicing is provided. The method includes dividing a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the method exposes the chip to a heated ambient environment having a given pressure (e.g., less than one atmosphere). The environment includes a chemical agent capable of bonding with the metallic substance. Additionally, wet chemical etch may be performed on the chip.Type: ApplicationFiled: December 13, 2007Publication date: June 18, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MUKTA G. FAROOQ, ROBERT HANNON, DAE-YOUNG JUNG
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Publication number: 20090155985Abstract: A method divides a wafer into at least one chip. The chip includes internal metallic features. The dividing deposits at least one metallic substance on the outer surface of the chip. After so dividing the chip, the process exposes the chip to a heated ambient environment having a given pressure (e.g., less than one atmosphere). The environment comprises a chemical agent capable of bonding with the metallic substance. Additionally, wet chemical etch can be performed on the chip.Type: ApplicationFiled: July 15, 2008Publication date: June 18, 2009Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Robert Hannon, Da-Young Jung
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Publication number: 20090032974Abstract: A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.Type: ApplicationFiled: July 31, 2007Publication date: February 5, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, Robert Hannon, Dae-Young Jung, Ian D. Melville
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INHIBITING DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES IN BACK END OF LINE STRUCTURES
Publication number: 20080277765Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael W. Lane, Xiao Hu Liu, Thomas M. Shaw, Mukta G. Farooq, Robert Hannon, Ian D. W. Melville -
Patent number: 7375021Abstract: A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad in an upper level of a semiconductor wafer, forming an insulating stack over the terminal copper pad, and patterning and opening a terminal via within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer is formed and patterned over the top of the insulating stack, and the bottom cap layer over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection is formed on a patterned portion of the BLM stack.Type: GrantFiled: April 4, 2006Date of Patent: May 20, 2008Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Mukta G. Farooq, Robert Hannon, Ian D. Melville