Abstract: Chip location identification using dummy solder bead(s) is disclosed. A structure may include an integrated circuit (IC) chip including a plurality of solder beads for electrically coupling the IC chip to other structure, and a chip location identifier including at least one dummy solder bead on the IC chip, the chip location identifier representing a unique location of the IC chip in a wafer prior to dicing. The structure allows location tracking of an IC chip within a wafer without any additional processing, space, or mask levels. The structure can also be evaluated (visually or electrically) at the packaging level.

Abstract: Methods of forming an aluminum-free wire bond pad and the pad so formed are disclosed. In one embodiment, the method includes forming an opening through a dielectric layer to a last metal of a chip; forming a tantalum nitride (TaN) layer over the chip and over the opening; removing the tantalum nitride (TaN) layer outside of the opening; forming a passivation mask layer over the chip including a passivation mask opening over the last metal; forming a titanium tungsten (TiW) layer and a copper (Cu) layer over the chip; forming a mask layer over the chip including a mask opening to the copper (Cu) layer over the last metal; forming a nickel (Ni) layer and a copper (Cu) layer and then a gold (Au) layer in the mask opening; and removing the mask.

Abstract: Via stack structures are disclosed. In one embodiment, a structure includes a via stack including: a first substantially cross-shaped line in a first dielectric layer; a second substantially cross-shaped line set in a second dielectric layer, and a via stud coupling the first substantially cross-shaped line to the second substantially cross-shaped line. In another embodiment, a structure includes a first via stack, and a second via stack, wherein the first via stack and the second via stack extend in a divergent manner from one another. Each via stack structure is useful for support, for example, in under wire bond applications. The via stack structures can be mixed with other via stack structures and selectively placed within a layout to replace conventional metal plate and via stud array configurations.

Abstract: A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad in an upper level of a semiconductor wafer, forming an insulating stack over the terminal copper pad, and patterning and opening a terminal via within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer is formed and patterned over the top of the insulating stack, and the bottom cap layer over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection is formed on a patterned portion of the BLM stack.

Abstract: An integrated circuit (IC) chip and related package are disclosed including a first interlevel dielectric (ILD) layer(s) including an ultra low dielectric constant (ULK) material, a second ILD layer(s) including a silicon dioxide (SiO2) based dielectric material above the first ILD layer(s), and a transitional ILD layer including an intermediate dielectric constant material. The transitional ILD layer is positioned directly below a lowermost one of the second ILD layer(s), excepting any isolation layer, which represents the layer most susceptible to failure. The intermediate dielectric constant material can have a dielectric constant and an elastic modulus greater than that of the ULK material and less than that of the SiO2 based dielectric material. Hence, the intermediate dielectric constant provides adequate electrical properties, but also absorbs more of the stress than the typical ULK material, which reduces the likelihood of failure. A method of forming the IC chip is also disclosed.

Abstract: A silicon-on-insulation (SOI) body contact is formed within a device region of an SOI substrate so that no space of the SOI substrate is wasted for implementing a body contact. The body contact is formed by epitaxially growing silicon and depositing polysilicon. An electrical device can be formed to overlie the body contact. Thus, no additional circuitry or conductive path is required to electrically connect a body contact and a device region. Also, the body contact provides a predictable electrical characteristics without sacrificing the benefits attained from using the SOI substrate and conservation surface space on the semiconductor die.

Abstract: A silicon-on-insulation (SOI) body contact is formed within a device region of an SOI substrate so that no space of the SOI substrate is wasted for implementing a body contact. The body contact is formed by epitaxially growing silicon and depositing polysilicon. An electrical device can be formed to overlie the body contact. Thus, no additional circuitry or conductive path is required to electrically connect a body contact and a device region. Also, the body contact provides a predictable electrical characteristics without sacrificing the benefits attained from using the SOI substrate and conservation surface space on the semiconductor die.

Abstract: A method for forming a semiconductor devices structure includes providing a semiconductor substrate, forming a deep trench continuously in the substrate to separate a first region from a second region, and then forming a silicon-on-insulator region in the first region while maintaining a non-silicon-on-insulator region in the second region. The deep trench has a depth which is at least as deep as the depth of the buried oxide in the substrate. The invention also includes a device structure resulting from the method.

Abstract: A semiconductor device structure including a substrate including at least one silicon-on-insulator substrate region and at least one non-silicon-on-insulator region. The at least one silicon-on-insulator region and at least one non-silicon-on-insulator region are formed in a pattern in the substrate. At least one trench is arranged in the vicinity of at least at a portion of a boundary between a silicon-on-insulator substrate region and the non-silicon-on-insulator substrate region. The at least one trench is arranged in at least one of the silicon-on-insulator region and the non-silicon-on-insulator region.

Abstract: Electronic packages made with a high area percent coverage of blanket metal may be prone to certain kinds of ceramic defects. In aluminum nitride, these defects may be related to decomposition of the liquid sintering aid. In this experiment, unique additions to the metallization prevented the formation of certain ceramic defects. Our approach involves a unique composition used in an existing process.

Abstract: A process for creating a substrate including bulk silicon regions and semiconductor-on-insulator regions. Regions of a surface of a bulk silicon substrate are recessed above regions where it is desired to create buried oxide regions in the substrate. Implant mask regions are formed on the surface of the substrate over regions where it is not desired to create buried oxide regions. Buried oxide regions are formed in the substrate under the recessed regions in the substrate.

Abstract: Electronic packages made with a high area percent coverage of blanket metal may be prone to certain kinds of ceramic defects. In aluminum nitride, these defects may be related to decomposition of the liquid sintering aid. In this experiment, unique additions to the metallization prevented the formation of certain ceramic defects. Our approach involves a unique composition used in an existing process.

Abstract: Shallow trench isolation is combined with optional deep trenches that are self-aligned with the shallow trenches, at the corners of the shallow trenches, and have a deep trench width that is controlled by the thickness of a temporary sidewall deposited in the interior of the shallow trench and is limited by the sidewall deposition thickness of the deep trench fill.

Abstract: A process for creating a substrate including bulk silicon regions and semiconductor-on-insulator regions. Regions of a surface of a bulk silicon substrate are recessed above regions where it is desired to create buried oxide regions in the substrate. Implant mask regions are formed on the surface of the substrate over regions where it is not desired to create buried oxide regions. Buried oxide regions are formed in the substrate under the recessed regions in the substrate. The implant mask regions are removed, leaving bulk silicon regions between the buried oxide regions.

Abstract: A portable soccer golf game in which the players arrange a course comprising a plurality of independent and successive stations each defined by a starting location and a goal location according to the available space and their particular skill level. The game is played by placing goals at the various goal locations, whereby a player kicks a soccer ball from the designated starting location along any desired path toward the given goal location with the intent of getting the ball in the goal. The player with the fewest number of kicks to complete the course is the winner.

Abstract: Electronic packages made with a high area percent coverage of blanket metal may be prone to certain kinds of ceramic defects. In aluminum nitride, these defects may be related to decomposition of the liquid sintering aid. In this experiment, unique additions to the metallization prevented the formation of certain ceramic defects. Our approach involves a unique composition used in an existing process.

Abstract: A low programming voltage anti-fuse formed by a MOSFET (or MOS) or by a deep trench (DT) capacitor structure is described. Lowering the programming voltage is achieved by implanting a dose of heavy ions, such as indium, into the dielectric directly on the substrate or indirectly through a layer of polysilicon. The programming voltage can also be lowered on the MOSFET/MOS capacitor anti-fuse by accentuating the corners of active areas and gate areas of the device with suitable layout masks during processing. Silicon active area corner rounding steps should also be avoided in the fabrication of the anti-fuse to reduce the programming voltage. In the DT capacitor, lowering the programming voltage may be achieved by implanting the node dielectric of the DT anti-fuse with heavy ions either directly or through a conformal layer of polysilicon deposited on it or after the first amorphous silicon recess step during the fabrication of the DT capacitor.

Abstract: Electronic packages made with a high area percent coverage of blanket metal may be prone to certain kinds of ceramic defects. In aluminum nitride, these defects may be related to decomposition of the liquid sintering aid. In this experiment, unique additions to the metallization prevented the formation of certain ceramic defects. Our approach involves a unique composition used in an existing process.

Abstract: A method and apparatus for flattening a ceramic body comprised primarily of an aluminum nitride system having a liquid phase additive necessary for low temperature sintering during a firing thereof is disclosed. The ceramic body is referred to as an aluminum nitride multilayer ceramic (AlN MLC). The method and apparatus include a support tile having a first coating on a contact surface thereof, the AlN MLC for being placed upon the contact surface of the support tile. A load flattening tile having a second coating on a contact surface thereof is provided, the load flattening tile for being placed with its coated surface upon and in contact with the AlN MLC. Lastly, a furnace is provided for heating the support tile, AlN MLC, and load flattening tile at temperatures greater than 1500.degree. C.

Abstract: A laser tool for securing or removing a component from a semiconductor substrate includes a light-transmissive bonding tip having an opening to accommodate a central portion of the component inner and outer walls of the tip being coated with a light reflective material, a portion of the end of the tip being coated with a light absorptive material, so that peripheral areas of the component are locally heated by the tip to mount or remove the component.