Abstract: Undersired glitches in output signals from TSPC-1 flip-flop circuits having an output stage comprising an node and a second node are removed by precharging the second node (prior to a clock transition) to a value desired at the output node during a period following the clock transition, and connecting the output node to the second node upon such clock transition. Corrective circuitry illustratively comprising two NMOS transistors added to the output stage and receiving an input reflecting the desired future output is active during a portion of the operating cycle when the output stage exhibits a high impedance tristate condition.

Abstract: A dual-modulus digital prescaler circuit having an extended period in which responses to a divider control indicating a possible modulus change must be made, such extended period permitting higher speed operation while suffering no penalty in manufacturing cost or increased power use. In embodiments comprising a dual modulus divider, a fixed-modulus divider and interconnected control logic, dual modulus divider state transitions giving rise to incrementing of fixed-modulus divider states are selected to be independent of short-term instabilities in divider control inputs. Identified critical state transitions associated with output signals from the dual modulus divider are constrained to occur at times prior to periods of insensitivity to stability of the dual-modulus control signal. Thus, timing of such output signals is determined so that there will be following time interval sufficient to provide desired stability of the modulus control signal for the next divide cycle.

Abstract: A selective call radio (300) includes receiver (200). The receiver in turn includes an antenna (202) for receiving a radio signal having a first operating frequency, an amplifier(204) coupled thereto for generating an amplified signal; and a frequency translation circuit (208). The frequency translation circuit includes a selectivity filter (212) and an integrated frequency conversion circuit (216). The selectivity is coupled to the amplified signal for generating a filtered signal. The integrated frequency conversion circuit is coupled to the filtered signal and is incorporated into at least one IC (integrated circuit). The integrated frequency conversion circuit includes an oscillator (220), a divider (224), and a mixer (218). A first input of the mixer is coupled to the filtered signal generated by the selectivity filter. The divider is coupled to the oscillator and its output is coupled to a second input of the mixer.

Abstract: Disclosed is a specific regulator of Ii protein expression or immunoregulatory function. Specifically disclosed are several forms of the specific regulator of Ii, including those which function through the formation of a duplex molecule with an RNA molecule encoding mammalian Ii protein to inhibit Ii protein synthesis at the translation level. This class includes copolymers comprised of nucleotide bases which hybridize specifically to the RNA molecule encoding mammalian Ii protein, and also expressible reverse gene constructs. In other aspects, the disclosure relates to MHC class II-positive antigen presenting cells containing a specific regulator of Ii expression. Such cells are useful, for example, in the display of autodeterminant peptides in association with MHC class II proteins. Compositions of the invention find application in methods for treating diseases, for example malignancies and autoimmune disorders, in a patient by enhancing immunological attack on undesired cells.

Abstract: A voltage comparator (10) includes a differential amplifier (12), a switched latch (32), and a switch (26). The voltage comparator (10) receives a first input signal (18) and a second input signal (20), and produces a first output (38) and a second output (40) by comparing the first and second input signals. A reset input (30) disables and enables the voltage comparator (10).

Abstract: A high-speed current switch (36) comprises a differential switch (14), a current source (12), an op-amp (32), a feedback switch (38), a hold capacitor (40), a biasing transistor (42), and a second current switch (44). The high-speed current switch (36) receives a complementary control signal (46) and a control signal (48), and generates an output current (26).

Abstract: A prescaler system (100) has a prescaler circuit (102) coupled to a divider (104), wherein the divider includes an improved dynamic flip flop divider (118). The divider (118) includes a TSPC nine-transistor D-flip-flop (10). The divider further includes a tenth transistor such as N channel device (41) having a source coupled to ground (43), a drain coupled to a junction between a drain of a P channel device (34) and a drain of another N channel device (37). The divider also includes an eleventh transistor such as N channel device (42) having a source coupled to ground and a drain coupled to a junction between the drain of a P channel device (35) and the drain of a N channel device (39), the junction providing a feedback signal to a N channel device (36), wherein the eleventh transistor further has a gate coupled to the output signal (/Q.sub.A).

Abstract: A synthesizer (100) is used for generating a plurality of synthesized clock signals (128, 156). The synthesizer includes a clock source (102) for generating a common frequency reference signal (103), and a clock generator (104) coupled to the common frequency reference signal for generating a plurality of generated clock signals (106, 108), wherein each of the plurality of generated clock signals is offset from each other by a predetermined phase offset (189, 192). In addition, the synthesizer includes a plurality of PLLs (Phase Locked Loops) (166-168) for generating a selected one of the plurality of synthesized clock signals, wherein each of the plurality of PLLs is coupled to, and operates from, a corresponding one of the plurality of generated clock signals, and wherein the predetermined phase offset between each of the plurality of generated clock signals is known to suppress noise between the plurality of PLLs operating therefrom.

Abstract: A phase-frequency detector (110) includes an output stage (300) and a control stage (200). The output stage includes a pump up switched current source (350), a pump down switched current sink (360), and a constant current source (325) that are coupled to a charge pump output node (111). The control stage generates, in response to a divided variable frequency signal (FV) (136) and a reference frequency signal (FR) (106), a pump up control signal (246) and a pump down control signal (216).

Abstract: A low input prescaler (800) that is responsive to input signals having low amplitude alternating current (AC) components includes a switched tunable prescaler (280) that generates a prescaler output signal (221) having a prescaler output frequency during an operational state of the prescaler and having a free-running frequency that is responsive to a tuning control signal (216) during a tuning state of the prescaler. A frequency comparator (235) generates a comparator output in response to a difference between a reference frequency and the prescaler output frequency. A prescaler tuner (290, 390) adjusts the tuning control signal in response to the comparator output during the tuning state to minimize the difference between the reference frequency and the prescaler output frequency, and holds the tuning control signal during the operational state. The prescaler is used in phase lock loops (200, 400, 600) and other circuits.

Abstract: A two's complement digital to analog converter (300) is for converting a two's complement binary value to an analog output current, and includes a control circuit (310) which generates controlled value bits, a digital to analog current converter (DACC) (320), and an augmenter (330). The DACC (320) generates a DACC analog current which is a portion of the analog output current and which has an absolute value which is related to the binary value of the controlled value bits. The augmenter (330), which is coupled to a most significant bit of the two's complement binary value, generates a portion of the analog output current by modifying the absolute value of the DACC analog current by a least significant bit current increment when the most significant bit indicates a negative value of the two's complement binary value.

Abstract: A method is used by a detector (102) for extending the operating frequency range of a phase lock loop (100). The detector (102) detects a phase-frequency difference between a reference signal (109) and a generated signal (108) of the phase lock loop (100). The detector (102) includes a divider (202) for counting transitions of the generated signal (108) and a logic element (204) and counter (212) for detecting when the frequency of the generated signal (108) is such that the divider (202) operates outside its linear frequency range in relation to a predetermined transition of the reference signal (109). The detector (102) further includes a register (206) for recording a phase value of the divider (202) coincident with the predetermined transition, or a constant phase value (304, 306) when the frequency of the generated signal (108) is operating outside of the linear range of the divider (202).

Abstract: A method for epoxidizing olefins is provided wherein an olefin and an oxygenating agent are contacted together in the presence of a manganese complex catalyst having at least one manganese atom coordinated with a nitrogen-containing ligand such that the manganese atom to coordinated nitrogen atom is 1:3 and thereafter isolating the resultant epoxide product. Catalyst compositions are also provided formed from the adsorption of the manganese complex catalyst onto a solvent insoluble support.

Abstract: A method for epoxidizing olefins is provided wherein an olefin and an oxygenating agent are contacted together in the presence of a manganese complex catalyst having at least one manganese atom coordinated with a nitrogen-containing ligand such that the manganese atom to coordinated nitrogen atom is 1:3 and thereafter isolating the resultant epoxide product. Catalyst compositions are also provided formed from the adsorption of the manganese complex catalyst onto a solvent insoluble support.

Abstract: A single stage energized fluid-flywheel comprises two concentric housings defining a main circulation chamber and an annular recirculation chamber surrounding the main circulation chamber. An axially extending shaft is rotatably mounted in the outer housing and has a series of blades mounted thereon. Upon rotation of the shaft, fluid is drawn by the blades into the inlet end of the main circulation chamber. The fluid is propelled from one series of blades to the next until it is discharged from the outlet end. The fluid is then redirected around the inner housing and recirculated through the recirculation chamber. The fluid, being constantly recirculated within the device will increase in speed or maintain the existing speed with relatively minimal force being applied to rotate the axially extending shaft. Toroidal shaped flow deflectors at opposing ends of the fluid flywheel facilitate smooth transition of fluid from the main circulation chamber to the recirculation chamber and vice versa.

Abstract: A viscous fluid timed infusion device having a cylindrical housing having an orifice in one end. A plunger is movable in the housing and spring means are operatively positioned in the housing to urge the plunger towards the orifice. A viscous fluid timing device controls rate of movement of the plunger towards the orifice.

Abstract: An arrangement and a method of prosthetically repairing teeth includes preparing a tooth by marking major surfaces thereof with scribe lines, and by removing tooth structure from the tooth in dependence upon the location of the scribe lines. An elongated recess is formed in the prepared tooth. A coping adapted for placement over the prepared tooth fits in the recess and is formed with a bore which extends in direction of the elongation of the recess. An artificial crown or cap adapted for placement over the coping is formed with a cavity which extends in direction of the elongation of the recess. A two-part detachable fastener has one part mounted in the bore of the coping and its other part mounted in the cavity of the cap. The mutual alignment of the bore and the cavity permits the cap to be secured to the coping with little play when the fastener parts are moved into fitting engagement with each other. The detachable fastener may be of snap-type or of magnetic-type.