Abstract: A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of 2:1. All the peripheral circuits are preferably disposed in the central connection area. As a result, the propagation time differences between the peripheral circuits and the various cell arrays are relatively small.

Abstract: Electrical fuses/antifuses in a semiconductor memory configuration, such as in particular a DRAM, are read, instead of with the previously conventional internal voltage, with the voltage that defines the high potential of the bit lines of a memory cell array in the semiconductor memory. The high potential of the bit lines is defined by a voltage that is reduced relative to the internal voltage of the semiconductor memory.

Abstract: An integrated semiconductor circuit has a transistor of the NMOS type that is disposed in a well of a p conductivity type in a substrate of the p conductivity type. The well is electrically insulated from the substrate. The semiconductor circuit furthermore contains a control circuit with a variable output signal. The well terminal of the transistor is connected to the output signal of the control circuit. The transistor is protected against permanent damage by virtue of its well potential being raised in a corresponding operating mode of the semiconductor circuit in which an increased operating voltage is applied to the transistor.

Abstract: A decontamination system including an absorptive/absorptive activated carbon felt pad saturated with a non-hazardous CWA decontamination solvent as nonspecific means of decontaminating equipment and open-wounds is provided. The entire system preferably includes an absorbent pad and decontamination fluid in a sealed, disposable plastic packet. The system is thus a simple and immediate means of personal decontamination. The decontamination fluid and the absorbent pads of the present invention are non-hazardous, nontoxic, and nonflammable. The system is thus safe, and able to readily meet with FDA approval. The system is small and easily corrected in a field pack or other means and can be safely disposed of after use. The same system is also useable at casualty receiving stations to decontaminate patients and/or equipment.

Abstract: A system for testing an integrated circuit at a plurality of locations with a plurality of test modes includes a sequence of test-mode storage devices, each of which has an input and an output. The sequence includes at least first and second test-mode storage devices located at corresponding first and second locations on the integrated circuit and configured to store first and second test modes. The first test-mode storage device is configured to perform a shift operation by providing the first test-mode at its output. The second test-mode storage device has its input connected to the output of the first test-mode storage device. This second device is configured to perform the shift operation by receiving, at its input, the first test mode and providing, at its output, the second test-mode.

Abstract: An integrated semiconductor circuit has a transistor of the NMOS type that is disposed in a well of a p conductivity type in a substrate of the p conductivity type. The well is electrically insulated from the substrate. The semiconductor circuit furthermore contains a control circuit with a variable output signal. The well terminal of the transistor is connected to the output signal of the control circuit. The transistor is protected against permanent damage by virtue of its well potential being raised in a corresponding operating mode of the semiconductor circuit in which an increased operating voltage is applied to the transistor.

Abstract: A filter system including a housing with an intake and an outlet, a pleated carbon filter disposed between the intake and the outlet for filtering out vapors entering the intake, and a hydrophobic solution dispersed about the pleated carbon filter to inhibit adsorption of water thereby increasing the adsorption capacity of the pleated carbon filter especially in high relative humidity environments. The hydrophobic solution is selected so that it does not decrease the adsorption capacity of the carbon filter. Also disclosed is a method of making such a filter.

Abstract: A method for supplying current to a semiconductor chip, particularly to a semiconductor memory chip, in which, in a standby mode, the semiconductor chip is supplied with current from a standby current generator, and in which, in a normal operating mode, the semiconductor chip is supplied with current from a normal mode current generator. The standby current generator provides a smaller current than the normal mode current generator, and where, in a product development phase, the semiconductor chip is supplied with current from the standby current generator in a test mode. The semiconductor chip is additionally to be supplied with current from the normal mode current generator in the product development phase.

Abstract: A method for testing semiconductor memory modules in which data are stored in banks with an addressable matrix structure containing rows and columns. Defect addresses of the defect locations in the banks are transmitted in compressed form to an external test device. The rows and/or the columns are subdivided into regions. The defects occurring in the respective region are counted row by row and/or column by column. The number of defects in each region is compared row by row and/or column by column with a threshold value, and the comparison results are transmitted as additional information row by row and/or column by column together with the defect addresses to a test device.

Abstract: In order to identify an integrated circuit, the bits of the chip ID are programmed by fuses or antifuses. Programming errors and aging errors can be detected and corrected by adding redundant bits. This can be applied in particular when electrically programmable fuses/antifuses are used in order to make the re-detection of a faulty chip ID more reliable.

Abstract: A method and a memory system temporarily store the addresses in a memory field during the writing-in of data. The addresses are applied to a write unit simultaneously with the data. Due to the intermediate storage of the addresses, the data can be input in a flexible manner, for example, even with a chronological delay in relation to the addresses.

Abstract: The invention relates to a semiconductor module having a plurality of signal paths for carrying external signals that each contain a setup and hold circuit on the basis of a latch circuit with a full latch and a logic circuit. The latch circuit contains at a beginning of the signal path upstream of the logic circuit a hold latch. The hold latch responds to the leading edge of a fast clock signal derived from the clock signal of the external signal, for the early latching of the external signal and for the decoupling of the hold time from the setup time. The full latch is disposed downstream of the logic circuit for the final latching of the external signal or of a signal derived from the latter.

Abstract: In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.

Abstract: An integrated semiconductor circuit has a transistor of the NMOS type that is disposed in a well of a p conductivity type in a substrate of the p conductivity type. The well is electrically insulated from the substrate. The semiconductor circuit furthermore contains a control circuit with a variable output signal. The well terminal of the transistor is connected to the output signal of the control circuit. The transistor is protected against permanent damage by virtue of its well potential being raised in a corresponding operating mode of the semiconductor circuit in which an increased operating voltage is applied to the transistor.

Abstract: The semiconductor component is provided for connection to a test system. An external clock signal with a modulated duty ratio can be input to the semiconductor component at a connection provided for that purpose on the semiconductor component. The latter has a clock recovery circuit, which obtains a periodic clock signal from the modulated clock signal, and a shift register, to which the modulated clock signal can be fed in a manner clocked by the periodic clock signal and which provides a data signal. The present invention makes it possible, in particular in mass memory chips, to feed in clock signals and also program, address or data signals for the realization of BIST via just one connection contact.

Abstract: An integrated circuit incorporating a self-test device and a method for producing a self-testing integrated circuit. The integrated circuit has a program memory with at least one external terminal for loading external test programs. The integrated circuit has a self-test device connected to the program memory, the self-test device executing program commands of a test program loaded into the program memory, the program commands succeeding one another in address terms, for carrying out a self-test of the circuit. The self-test device has an interrupt signal input, through which the self-test device interrupts the test program that is currently being executed by not executing the respective succeeding program command in address terms. Rather, it executes a program jump within the test program, the program jump being triggered by the interrupt signal.

Abstract: An integrated circuit includes a data processing unit, a buffer memory, and a setting memory. The buffer memory performs the function of registers for storing data for the processing unit. The buffer memory is connected to the setting memory. The setting memory can be written to through the buffer memory.

Abstract: A refresh drive circuit for feeding refresh signals to a memory device has a refresh signal generator for generating a continuous sequence of refresh signals with a frequency which decreases as the temperature falls. The refresh drive circuit is connected to the memory device and as the temperature of the memory device falls, the frequency of refresh cycles decreases resulting in a decrease in current consumption.

Abstract: A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of 2:1. All the peripheral circuits are preferably disposed in the central connection area. As a result, the propagation time differences between the peripheral circuits and the various cell arrays are relatively small.

Abstract: A circuit includes a programmable element having conductor track resistance that can be permanently altered by an electric current. The circuit also has a switchable element for receiving a control signal for programming the programmable element. The programmable element and the switchable element are connected in series between two supply potentials. The programmable element can have an electrical fuse. The input of a read-out circuit is connected through a protective circuit to the circuit node between the programmable element and the switchable element. The protective circuit serves for limiting the voltage potential at the input of the read-out circuit during a programming operation. The circuit elements of the read-out circuit can thus be dimensioned in an area-saving manner. The protective circuit also can include a diode having an anode connected to the input of the read-out circuit and a cathode connected to a third supply potential.