Abstract: The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

Abstract: The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

Abstract: The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

Abstract: The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

Abstract: The present disclosure includes apparatuses and methods for counter update operations. An example apparatus comprises a memory including a managed unit that includes a plurality of first groups of memory cells and a second group of memory cells, in which respective counters associated with the managed unit are stored on the second group of memory cells. The example apparatus further includes a controller. The controller includes a core configured to route a memory operation request received from a host and a datapath coupled to the core and the memory. The datapath may be configured to issue, responsive to a receipt of the memory operation request routed from the core, a plurality of commands associated with the routed memory operation request to the memory to perform corresponding memory operations on the plurality of first groups of memory cells. The respective counters may be updated independently of the plurality of commands.

Abstract: A system is disclosed for centralized management of access permissions to specific devices on client terminals using a group policy framework. The system identifies a unique device identifier for a specific device, and allows policy to be set for the specific device based on identifying the specific device by its unique device identifier.

Abstract: A biometric-based security circuit in which the user database, processor, and biometric map generation functions are all located on the same integrated circuit whose secure contents are inaccessible from external to the integrated circuit. Biometric data, such as a fingerprint, retina scan, or voiceprint, is taken from a user requesting access to restricted resources. The biometric data is transferred into the integrated circuit, where it is converted to a biometric map and compared with a database of biometric maps stored in a non-volatile memory in the integrated circuit. The stored maps represent pre-authorized users, and a match triggers the security circuit to send a signal to a host processor authorizing the host processor to permit the requesting user access to the restricted resources.

Abstract: A system is disclosed for centralized management of access permissions to specific devices on client terminals using a group policy framework. The system identifies a unique device identifier for a specific device, and allows policy to be set for the specific device based on identifying the specific device by its unique device identifier.

Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. A method of reliably re-allocating a first object includes the step of storing a location of a first object in a first data structure. A location of the first data structure is stored in a second data structure. A duplicate of the first object is formed by initiating a copy of the first object. An erase of the first object is initiated. A write of a second object to the location of the first object is then initiated. The duplicate object is invalidated. The status of copying, erasing, and writing is tracked. The copy status, erase status, write status, and a restoration status are used to determine a recovery state upon initialization of the nonvolatile memory. The duplicate object is invalidated, if the writing status indicates that the writing of the second object has been completed.

Abstract: A method and device for providing hidden storage in non-volatile memory. A memory device is disclosed comprising a main flash array. A hidden storage area is connected to the main flash array. The hidden storage area can not be accessed without a valid password according to the present memory device.

Abstract: Methods for storing data in an erasable nonvolatile memory are described herein. In one embodiment, an example method includes allocating a space within a block of an erasable nonvolatile memory for an object, wherein the allocated space is within a single block of the erasable nonvolatile memory and the allocated space includes a plurality of areas capable of storing multiple instances of the object, storing a first instance of the object in one of the areas within the allocated space, storing a superseding second instance of the object in another one of the areas within the allocated space without erasing any of the allocated space, and for each of the first and second instances of the object, storing status information corresponding to the respective instance of the object within the allocated space which is within the single block of the erasable nonvolatile memory.

Abstract: A method wherein a special programming mode of a memory is entered. The special programming mode disables internal verification by the memory. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. A host processor verifies external to the memory the programming of the plurality of data words into the memory. The special programming mode is exited and internal program verification by the memory is enabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry.

Abstract: A biometric-based security circuit in which the user database, processor, and biometric map generation functions are all located on the same integrated circuit whose secure contents are inaccessible from external to the integrated circuit. Biometric data, such as a fingerprint, retina scan, or voiceprint, is taken from a user requesting access to restricted resources. The biometric data is transferred into the integrated circuit, where it is converted to a biometric map and compared with a database of biometric maps stored in a non-volatile memory in the integrated circuit. The stored maps represent pre-authorized users, and a match triggers the security circuit to send a signal to a host processor authorizing the host processor to permit the requesting user access to the restricted resources.

Abstract: A biometric-based security circuit in which the user database, processor, and biometric map generation functions are all located on the same integrated circuit whose secure contents are inaccessible from external to the integrated circuit. Biometric data, such as a fingerprint, retina scan, or voiceprint, is taken from a user requesting access to restricted resources. The biometric data is transferred into the integrated circuit, where it is converted to a biometric map and compared with a database of biometric maps stored in a non-volatile memory in the integrated circuit. The stored maps represent pre-authorized users, and a match triggers the security circuit to send a signal to a host processor authorizing the host processor to permit the requesting user access to the restricted resources.

Abstract: A method wherein a special programming mode of a memory is entered. The special programming mode disables internal verification by the memory. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. Hashing is performed with respect to the plurality of data words to generate a first hash value. The host processor compares the first hash value with a second hash value to see whether the first and second hash values are the same or different. The special programming mode is exited and internal program verification by the memory is enabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry.

Abstract: A method and device for providing hidden storage in non-volatile memory. A memory device is disclosed comprising a main flash array. A hidden storage area is connected to the main flash array. The hidden storage area can not be accessed without a valid password according to the present memory device.

Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. A method of reliably re-allocating a first object includes the step of storing a location of a first object in a first data structure. A location of the first data structure is stored in a second data structure. A duplicate of the first object is formed by initiating a copy of the first object. An erase of the first object is initiated. A write of a second object to the location of the first object is then initiated. The duplicate object is invalidated. The status of copying, erasing, and writing is tracked. The copy status, erase status, write status, and a restoration status are used to determine a recovery state upon initialization of the nonvolatile memory. The duplicate object is invalidated, if the writing status indicates that the writing of the second object has been completed.

Abstract: A method and device for providing hidden storage in non-volatile memory. A memory device is disclosed comprising a main flash array. A hidden storage area is connected to the main flash array. The hidden storage area can not be accessed without a valid password according to the present memory device.

Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. A method of reliably re-allocating a first object includes the step of storing a location of a first object in a first data structure. A location of the first data structure is stored in a second data structure. A duplicate of the first object is formed by initiating a copy of the first object. An erase of the first object is initiated. A write of a second object to the location of the first object is then initiated. The duplicate object is invalidated. The status of copying, erasing, and writing is tracked. The copy status, erase status, write status, and a restoration status are used to determine a recovery state upon initialization of the nonvolatile memory. The duplicate object is invalidated, if the writing status indicates that the writing of the second object has been completed.

Abstract: A memory module including a flash EEPROM memory array designed to be joined to a memory bus of a computer, BIOS processes including system status test processes stored in the array, diagnostic processes stored in the array to provide data indicating malfunctions in the computer, accessing processes stored in the array for calling the system status test processes and the diagnostic processes even though the computer fails to boot, and communication processes stored in the array for transferring results produced by the system status test processes and the diagnostic processes for use in servicing the computer.