Patents by Inventor Robert N. Hasbun
Robert N. Hasbun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020083381Abstract: A method wherein a special programming mode of a memory is entered. The special programming mode disables internal verification by the memory. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. A host processor verifies external to the memory the programming of the plurality of data words into the memory. The special programming mode is exited and internal program verification by the memory is enabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry.Type: ApplicationFiled: December 26, 2000Publication date: June 27, 2002Inventors: Lance W. Dover, Robert N. Hasbun, Paul D. Ruby, William T. Reaves
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Publication number: 20020083385Abstract: A method wherein a special programming mode of a memory is entered. The special programming mode disables internal verification by the memory. The memory includes automation circuitry for program verification. A plurality of words is programmed into the memory without the memory performing internal program verification. Hashing is performed with respect to the plurality of data words to generate a first hash value. The host processor compares the first hash value with a second hash value to see whether the first and second hash values are the same or different. The special programming mode is exited and internal program verification by the memory is enabled. An apparatus is also described having a host processor and a memory with special programming mode circuitry.Type: ApplicationFiled: December 26, 2000Publication date: June 27, 2002Inventors: Lance W. Dover, Robert N. Hasbun, Paul D. Ruby, William T. Reaves
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Patent number: 6412040Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. In one embodiment, a method of reliably re-allocating a first object stored within a block erasable nonvolatile memory includes the step of allocating space for a second object. A write of the second object is initiated and the writing of the second object is tracked. In another embodiment, a method of re-allocating a first object stored within a block erasable nonvolatile memory includes the step of invalidating the first object, if the first object has an unreliable type of recovery level. Space is allocated for the second object. A write of the second object is initiated and the writing of the second object is tracked. In another embodiment, a method of reliably re-allocating a first object stored within the block erasable nonvolatile memory includes the step of allocating space for the second object.Type: GrantFiled: January 20, 2000Date of Patent: June 25, 2002Assignee: Intel CorporationInventors: Robert N. Hasbun, David A. Edwards
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Patent number: 6401160Abstract: A method of moving a boundary in a nonvolatile memory is disclosed. The method comprises identifying a boundary location in the nonvolatile memory. The boundary location comprises a position between a first block of a first type and a second block of a second type. The method also comprises allocating objects from a last block of the first type to a second block of the first type. Additionally, the method comprises erasing the last block of the first type.Type: GrantFiled: March 31, 1999Date of Patent: June 4, 2002Assignee: Intel CorporationInventors: Deborah L. See, Robert N. Hasbun
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Publication number: 20010042158Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. In one embodiment, a method of reliably re-allocating a first object stored within a block erasable nonvolatile memory includes the step of allocating space for a second object. A write of the second object is initiated and the writing of the second object is tracked. In another embodiment, a method of re-allocating a first object stored within a block erasable nonvolatile memory includes the step of invalidating the first object, if the first object has an unreliable type of recovery level. Space is allocated for the second object. A write of the second object is initiated and the writing of the second object is tracked. In another embodiment, a method of reliably re-allocating a first object stored within the block erasable nonvolatile memory includes the step of allocating space for the second object.Type: ApplicationFiled: January 20, 2000Publication date: November 15, 2001Inventors: ROBERT N. HASBUN, DAVID A. EDWARDS
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Patent number: 6311290Abstract: Methods of reliably allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. Allocation, writing, reading, de-allocating, re-allocating, and reclamation are handled by a memory manager. The memory manager tracks the progress of each process during execution in order to detect whether a selected process was interrupted for purposes of recovery. The nonvolatile memory is recovered to a known state during initialization. Initialization includes the step of determining a recovery state from a recovery state lookup table. A selected recovery process is selected in accordance with the recovery state lookup table. A restart level for the selected process is determined from a corresponding restart state lookup table. The selected process is then restarted at the restart level.Type: GrantFiled: April 3, 1998Date of Patent: October 30, 2001Assignee: Intel CorporationInventors: Robert N. Hasbun, David A. Edwards, Andrew H. Gafken, Christopher J. Spiegel
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Patent number: 6295619Abstract: A method for storing data in a memory partitions the memory into a plurality of partitions. A primary logical identifier is stored in the memory to identify each partition of data. A secondary identifier number is also stored in the memory to identify each partition of data, the secondary logical identifier redundant to the primary logical identifier. A primary logical identifier is used to locate at least one partition of data stored in the memory after receiving a requested partition number identifying a requested partition. The secondary logical identifier is used to compute a value to further identify the at least one partition of data. The value is computed by performing a logical AND operation between the primary logical identifier and the secondary logical identifier. This value is compared with the requested partition number. A method of detecting column short bit locations in a memory arranged as m words of n bits of memory.Type: GrantFiled: November 24, 1998Date of Patent: September 25, 2001Assignee: Intel CorporationInventors: Robert N. Hasbun, Daniel H. Leemann
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Patent number: 6243789Abstract: A method of executing a program includes the step of initiating execution of the program stored contiguously without code fragmentation in a nonvolatile memory. Execution of the program is halted if the program attempts to modify a page of the nonvolatile memory. The page of nonvolatile memory is then copied to a modifiable memory. The page of nonvolatile memory is then remapped to the modifiable memory. Execution of the program is then resumed. A computer system for execution of a program includes a nonvolatile memory storing a program contiguously without code fragmentation. The computer system includes a processor for executing the program. A memory management unit generates an interrupt in response to a request to modify a page of the nonvolatile memory. Execution of the program is halted and the processor copies the page of nonvolatile memory to a modifiable memory in response to the interrupt.Type: GrantFiled: February 23, 1998Date of Patent: June 5, 2001Assignee: Intel CorporationInventors: Robert N. Hasbun, David A. Edwards
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Patent number: 6226728Abstract: A method of storing data in a nonvolatile memory includes the step of receiving the data to be stored. A storage structure is selected for the data according to the relative size (z) of the data with respect to a plurality of thresholds including: a minimum number of instances (m), a maximum single instance size (s*g), and an allocation granularity (g). The data is then stored in the selected structure within the nonvolatile memory. If z is less than a first threshold, the data is stored within a multiple instance object structure. If z is less than a second threshold, the data is stored as a single instance object. If z exceeds the second threshold, the data is fragmented. The fragmented data can then be stored among the plurality of blocks of nonvolatile memory. If the number of fragments is less than a maximum sequence table size, then a sequence table indicative of the order and the locations of the data fragments is stored in the nonvolatile memory.Type: GrantFiled: April 21, 1998Date of Patent: May 1, 2001Assignee: Intel CorporationInventors: Deborah L. See, Robert N. Hasbun, Jeffrey A. Dunlap, Phillip J. del Pozo, III
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Patent number: 6223290Abstract: A method and apparatus for controlling use of an electronic system is described. Use of the electronic system is controlled by programming at least one unique code into an auxiliary memory of the electronic system. The auxiliary memory is a permanently lockable memory that is located outside of a main memory array space. The unique code is compared to at least one component code. Use of the electronic system is controlled based on a predefined relationship between the unique code and the component code.Type: GrantFiled: May 7, 1998Date of Patent: April 24, 2001Assignee: Intel CorporationInventors: Robert E. Larsen, Peter K. Hazen, Sandeep K. Guliani, Robert N. Hasbun, Sanjay S. Talreja, Collin Ong, Charles W. Brown, Terry L. Kendall
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Patent number: 6205548Abstract: Code is written to a selected portion of a nonvolatile memory having a first portion associated with a first range of addresses and a second portion associated with a second range of addresses, wherein the selected portion is the second portion. Toggling a block selector swaps addresses of the first and second portions, wherein the first range of addresses reference the second portion of nonvolatile memory and the second range of addresses reference the first portion of nonvolatile memory. An apparatus includes a processor that initiates a boot sequence at a pre-determined address. An address decoder accesses a one of a first and a second block of nonvolatile memory in response to the pre-determined address in accordance with a value of the block selector. A method using a group selector includes the step of receiving an address from a processor. The address is decoded to access one of a first and a second group of blocks of nonvolatile memory in accordance with a value of the group selector.Type: GrantFiled: July 31, 1998Date of Patent: March 20, 2001Assignee: Intel CorporationInventor: Robert N. Hasbun
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Patent number: 6189070Abstract: A method and apparatus manages data and reads code from a nonvolatile writeable memory. In a nonvolatile writeable system, interrupts are disabled. A non-read operation is initiated in the nonvolatile writeable memory. A check for whether an interrupt has occurred is performed. If an interrupt has occurred, then the non-read operation in the nonvolatile writeable memory is suspended. Interrupts are enabled, and code is read from the nonvolatile writeable memory. Non-read operations may include program operations and erase operations.Type: GrantFiled: August 28, 1997Date of Patent: February 13, 2001Assignee: Intel CorporationInventors: Deborah L. See, Robert N. Hasbun
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Patent number: 6182188Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. A method of reliably re-allocating a first object includes the step of storing a location of a first object in a first data structure. A location of the first data structure is stored in a second data structure. A duplicate of the first object is formed by initiating a copy of the first object. An erase of the first object is initiated. A write of a second object to the location of the first object is then initiated. The duplicate object is invalidated. The status of copying, erasing, and writing is tracked. The copy status, erase status, write status, and a restoration status are used to determine a recovery state upon initialization of the nonvolatile memory. The duplicate object is invalidated , if the writing status indicates that the writing of the second object has been completed.Type: GrantFiled: April 6, 1997Date of Patent: January 30, 2001Assignee: Intel CorporationInventors: Robert N. Hasbun, David A. Edwards, Andrew H. Gafken, Christopher J. Spiegel
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Patent number: 6154819Abstract: An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits.Type: GrantFiled: May 11, 1998Date of Patent: November 28, 2000Assignee: Intel CorporationInventors: Robert E. Larsen, Peter Hazen, Sanjay S. Talreja, Sandeep Guliani, Robert N. Hasbun, Collin Ong, Terry D. West, Charles Brown, Terry L. Kendall
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Patent number: 6088759Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. In one embodiment, a method of reliably re-allocating a first object stored within a block erasable nonvolatile memory includes the step of allocating space for a second object. A write of the second object is initiated and the writing of the second object is tracked. In another embodiment, a method of re-allocating a first object stored within a block erasable nonvolatile memory includes the step of invalidating the first object, if the first object has an unreliable type of recovery level. Space is allocated for the second object. A write of the second object is initiated and the writing of the second object is tracked. In another embodiment, a method of reliably re-allocating a first object stored within the block erasable nonvolatile memory includes the step of allocating space for the second object.Type: GrantFiled: June 30, 1997Date of Patent: July 11, 2000Assignee: Intel CorporationInventors: Robert N. Hasbun, David A. Edwards
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Patent number: 6014755Abstract: A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.Type: GrantFiled: August 12, 1996Date of Patent: January 11, 2000Assignee: Intel CorporationInventors: Steven E. Wells, Eric J. Magnusson, Robert N. Hasbun
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Patent number: 5937434Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. A method of storing an object within a managed object space of the nonvolatile memory includes the step of determining an object class for the object. Objects of a first class are stored contiguously proceeding from a first end towards a second end of the managed object space to form a first class of space. Objects of a second class are stored contiguously proceeding from the second end towards the first end of managed object space to form a second class of space. A header identifying the object is stored at a bottom of the first class of space. The object is stored at a selected one of the bottom of the first class of space and a bottom of the second class of space in accordance with the object class.Type: GrantFiled: February 14, 1997Date of Patent: August 10, 1999Assignee: Intel CorporationInventors: Robert N. Hasbun, David A. Edwards, Andrew H. Gafken
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Patent number: 5936884Abstract: A method of performing multiple writes before erasing a memory cell is described. M bits are stored in a first group of levels of the memory cell. M subsequent superseding bits are stored in a second group of levels of the memory cell without erasing the memory cell. Another method of writing to a memory cell includes the step of storing m bits in a first group of levels of the memory cell. A group indicator is adjusted to identify a subsequent group of levels of the memory cell. Next, m superseding subsequent bits are stored in the subsequent group of levels, without erasing the memory cell. The steps of adjusting the group indicator and storing m superseding subsequent bits are repeated. A method of deferring an erase for a memory cell is also described. A group indicator is adjusted to identify a group of 2.sup.m adjacent levels of the memory cell available for storing an m bit value. A method of reading a memory cell includes providing a group indicator. The group indicator identifies a group of 2.sup.Type: GrantFiled: July 22, 1996Date of Patent: August 10, 1999Assignee: Intel CorporationInventors: Robert N. Hasbun, Frank P. Janecek
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Patent number: 5893135Abstract: An arrangement for accessing a non-volatile memory array including providing a signal having a first condition if an access is a read and a second condition if an access is for any other operation; reading data directly from an address in the non-volatile memory array if the signal is a first condition; and performing any other access of the non-volatile memory array utilizing a command-centric interface if the signal is a second condition.Type: GrantFiled: December 27, 1995Date of Patent: April 6, 1999Assignee: Intel CorporationInventors: Robert N. Hasbun, Andrew H. Gafken
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Patent number: 5875477Abstract: A method of accessing a memory includes the step of partitioning the memory into a plurality of partitions. A primary logical identifier is stored in the memory to identify each partition. A redundant secondary logical identifier is also stored in the memory to identify each partition. In response to a requested partition number identifying a partition to access, at least one partition of data is located using a first stored logical identifier formed from a portion of each of the primary and secondary logical identifiers. The at least one partition of data is then identified using a second stored logical identifier formed from a portion of at least one of the primary and secondary logical identifiers. In one embodiment, a first error detection code (EDC) stored in the header is used to validate the partition data. If an error is detected, the validity of the partition data is tested using an EDC computed by ANDing the first EDC and a second EDC stored in the header.Type: GrantFiled: December 22, 1995Date of Patent: February 23, 1999Assignee: Intel CorporationInventors: Robert N. Hasbun, Daniel H. Leemann