Patents by Inventor Robert N. Hasbun

Robert N. Hasbun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5867721
    Abstract: A circuit for selecting a select line from a plurality of first and second select lines is described. Each of an array of integrated circuit (IC) packages is coupled to (1) one of the first select lines and (2) at least one of the second select lines. The circuit includes a decoder for decoding a select data to select the select line, and circuitry for modifying the select data before the select data is applied to the decoder when each of the second select lines is not coupled to an IC device within each of the IC packages to ensure that the select line is not one of the second select lines. When each of the first and second select lines is coupled to an IC device within each of the IC packages, the circuitry for modifying does not modify the select data. A method for selecting a selected IC device within a selected IC package of an array of IC packages is also described.
    Type: Grant
    Filed: November 28, 1997
    Date of Patent: February 2, 1999
    Assignee: Intel Corporation
    Inventors: Mark P. Leinwander, Steven E. Wells, Robert N. Hasbun
  • Patent number: 5829013
    Abstract: Method and apparatus for executing a program stored in a non-volatile memory are disclosed. A method of executing a program includes the step of initiating execution of a program stored in a non-volatile memory. An exception is generated if a program command attempts to write to a location within the non-volatile memory. In response to the exception, a portion of the contents of the non-volatile memory including the location is relocated to a main memory with a program status of read/write/execute. The program is restarted at the program command causing the exception. An apparatus for executing a program stored in a non-volatile memory includes a main memory. The non-volatile memory is coupled to a main memory bus of the main memory. The program stored in the non-volatile memory has a read/execute program status. A processor is coupled to the main memory bus.
    Type: Grant
    Filed: December 26, 1995
    Date of Patent: October 27, 1998
    Assignee: Intel Corporation
    Inventor: Robert N. Hasbun
  • Patent number: 5822256
    Abstract: A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.
    Type: Grant
    Filed: March 5, 1997
    Date of Patent: October 13, 1998
    Assignee: Intel Corporation
    Inventors: Mark E. Bauer, Steven Wells, David M. Brown, Johnny Javanifard, Sherif Sweha, Robert N. Hasbun, Gary J. Gallagher, Mamun Rashid, Rodney R. Rozman, Glen Hawk, George Blanchard, Mark Winston, Richard D. Pashley
  • Patent number: 5822781
    Abstract: A solid state memory disk that stores data on a sector basis is described. The solid state disk includes an array of FLASH memory devices, which store the sectors of data. Each block of memory within the FLASH array includes data space for storing many sectors of data and a block sector translation table. The block sector translation table identifies each sector of data stored in the block's data space by a sector number. The solid state disk also includes a controller. Among its many responsibilities, the controller manages the writing of sector data into the array and the reading of sectors of data from the array. The controller responds to a write request by seeking an earlier version of the sector which has a logical sector number equal to the sector's sector number and marking that sector dirty. Afterward, the controller allocates free memory space for the sector of data. The sector of data is then written into the allocated memory space.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: October 13, 1998
    Assignee: Intel Corporation
    Inventors: Steven Wells, Robert N. Hasbun, Kurt Robinson
  • Patent number: 5815434
    Abstract: A method for performing multiple writes before an erase to a nonvolatile memory cell is described. A first bit is stored at a first level of a nonvolatile memory cell. A second bit is stored at a second level of the nonvolatile memory cell. A method of erasing a nonvolatile memory cell is described. A level indicator that indicates the next level of the nonvolatile memory cell to write to is incremented. A method of reading a nonvolatile memory cell includes recalling a level indicator. The nonvolatile memory cell is then sensed at a level indicated by the level indicator to determine the state of the memory cell.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: September 29, 1998
    Assignee: Intel Corporation
    Inventors: Robert N. Hasbun, Frank P. Janecek
  • Patent number: 5765002
    Abstract: A flash electrically-erasable programmable read only memory (EEPROM) device including a flash EEPROM array having circuitry for controlling operations within the flash EEPROM array, a microprocessor for controlling operations external to the flash EEPROM array, circuitry for detecting when operations are taking place within the array, and circuitry for disabling the microprocessor during periods in which operations are taking place in the flash EEPROM array so that power use by the microprocessor is minimized.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: June 9, 1998
    Assignee: Intel Corporation
    Inventors: Richard P. Garner, Robert N. Hasbun
  • Patent number: 5740349
    Abstract: A controller for controlling associated circuitry which includes a microprocessor, read only memory for storing control processes to be run by the microprocessor for controlling the associated circuitry, random access memory, and means for accessing the associated circuitry, by a process which detects changes in the associated circuitry during operation of the associated circuitry, and writes those changes to the read only memory so that they are available to the controller should power be lost during the operation of the associated circuitry.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 14, 1998
    Assignee: Intel Corporation
    Inventors: Robert N. Hasbun, Steven E. Wells
  • Patent number: 5740395
    Abstract: A method of cleaning-up a solid state memory disk is described. Clean-up begins with the selection of a focus block for clean-up. Next, on a sector-by-sector basis, memory is allocated within a destination block to store valid sectors of user data. User data is then copied into the destination block on a sector-by-sector basis. Afterward, the focus block is erased, converting dirty sectors into free memory without loss of valid sectors of data.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: April 14, 1998
    Assignee: Intel Corporation
    Inventors: Steven Wells, Robert N. Hasbun
  • Patent number: 5696929
    Abstract: A flash EEPROM memory array including a cache buffer for storing lines of data being written to all addresses in main memory; a plurality of holding buffers for storing lines of data from the cache buffer addressed to a particular block of addresses in main memory; a plurality of blocks of flash EEPROM main memory for storing lines of data from a holding buffer directed to a particular block of addresses in main memory; and control circuitry for writing lines of data addressed to a particular block of addresses in main memory from the cache buffer to a holding buffer when the cache buffer fills or a holding buffer limit is reached whichever occurs first, writing valid data from an addressed block of flash memory to lines of the holding buffer not holding valid data written from the cache buffer, erasing the addressed block of flash memory, and writing all of the lines in the holding buffer to the addressed block of flash memory.
    Type: Grant
    Filed: October 3, 1995
    Date of Patent: December 9, 1997
    Assignee: Intel Corporation
    Inventors: Robert N. Hasbun, Asad Faizi, Joann Lam, Peter J. Ruscito
  • Patent number: 5671388
    Abstract: A memory contains a plurality of memory cells that are capable of storing one or more bits of data in each memory cell. The memory stores, in response to a write operation, data corresponding to the write operation in a first set of the memory cells such that each cell of the first set of the memory cells stores a single bit. Thereafter, data from the first set of memory cells are transferred to a second set of the memory cells such that each cell of the second set of the memory cells stores more than a single bit of data. The write operation to the first set of cells is executed in a foreground operation, and in a subsequent background operation, data from the first set of memory cells are transferred to the second set of memory cells. The memory cells are non-volatile flash electrically erasable programmable read only memory (EEPROM) cells, and therefore require erasure before programming. Typically, memory cells are reclaimed in a background operation.
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: September 23, 1997
    Assignee: Intel Corporation
    Inventor: Robert N. Hasbun
  • Patent number: 5640529
    Abstract: A system and method for converting invalid user data within a solid state disk into free memory during time allotted to execute a host command from a standard interface. Clean-up states are part of a clean-up state machine which controls the conversion of the invalid user data into free memory. Whenever a command interrupt is received from the standard interface, a watchdog timer is set to the maximum time allotted to execute the command. The command is executed first, and then a number of clean-up states to be executed in the remaining time is calculated. A counter is set equal to that number. Thereafter, a clean-up state is executed and the counter is decremented. Execution of clean-up states and decrementing of the counter continues until either the counter indicates all states have been executed or the timer indicates that all allotted time has expired.
    Type: Grant
    Filed: September 16, 1996
    Date of Patent: June 17, 1997
    Assignee: Intel Corporation
    Inventor: Robert N. Hasbun
  • Patent number: 5586285
    Abstract: A solid state memory disk with increased reserve memory is described. The solid state memory disk includes an array of solid state memory devices for storing user data and reserve memory, which includes both free memory and dirty memory. The solid state memory disk also includes a controller, a clean-up state machine, and a data compressor. The data compressor increases reserve memory by compressing data received from a host and coupling compressed data to the array of memory devices under the control of the controller. In response to write commands from the host, the controller writes a first sector data, which has been compressed, to a first location in a first block within a memory device. Reserve memory within the array is thus increased, so long as the maximum number of sectors the host is allowed to write is less the average compression ratio of the data compressor multiplied by the capacity of the solid state disk. A method of increasing reserve memory in a solid state disk is also described.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: December 17, 1996
    Assignee: Intel Corporation
    Inventors: Robert N. Hasbun, Steven Wells
  • Patent number: 5581723
    Abstract: A method for reliably storing management data in a flash EEPROM memory array, which array is divided into a plurality of individually-erasable blocks of memory cells and in which each of the blocks of memory cells has stored thereon data regarding management of the array during a cleanup process in which valid data stored in a first block is written to another block of the array, and then the first block is erased. The process includes the steps of storing data regarding management of the array from the first block in random access memory and, in an enhanced process, on another block before erasure of the first block. The data may then be rewritten to the first block after the erase.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: December 3, 1996
    Assignee: Intel Corporation
    Inventors: Robert N. Hasbun, Steven E. Wells
  • Patent number: 5577194
    Abstract: A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: November 19, 1996
    Assignee: Intel Corporation
    Inventors: Steven E. Wells, Eric J. Magnusson, Robert N. Hasbun
  • Patent number: 5553261
    Abstract: A method of executing states of a clean-up state machine while executing a command from a host CPU to read a sector of data stored within a memory array. First, a number of sectors of data are copied from the memory array into a sector buffer. Then, while the host CPU is reading sectors from the sector buffer, a number of states of a clean-up state machine are executed to aid in the conversion of invalid user data into free memory. Also described is a solid state memory disk that converts invalid sectors of data to free memory while executing a read command from a host CPU.
    Type: Grant
    Filed: April 1, 1994
    Date of Patent: September 3, 1996
    Assignee: Intel Corporation
    Inventors: Robert N. Hasbun, Richard P. Garner
  • Patent number: 5544312
    Abstract: A method of protecting the accuracy of sector of data while the writing the sector of data into a block of a solid state memory disk. First, a sector offset is written into the block to indicate where within the data space of the block the sector data will be located. Second, the sector of data is written into the block. Afterward, the logical sector number that identifies the sector of data is written into the block in two steps. The first step in writing the logical sector number is to write a selected invalid logical sector number into the block. Next, the selected invalid sector number is converted into the valid sector number by programming a power-off bit of the selected invalid logical sector number. Thus, whenever power to the solid state disk is next turned on, the loss of a sector of data and the validity of the sector of data can be determined. The loss of a sector of data is identified by locating a header in the block whose only valid data is the sector offset.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: August 6, 1996
    Assignee: Intel Corporation
    Inventors: Robert N. Hasbun, Mark Christopherson
  • Patent number: 5535369
    Abstract: A method of allocating free physical memory in a solid state memory disk for a sector of data of a given size is described. Allocation begins by determining whether sufficient free memory remains in the block to which the previous sector of data was written. If there is not sufficient free memory remaining, then selection of another block to allocate the sector of data begins. The selection is based on the sum of the amount of free memory in a selected block and one of the following: 1) the amount of invalid data in the block; 2) the cycle count for the block; 3) the amount of invalid data as compared to a maximum amount of invalid data for all non-volatile memory devices associated with the block; and 4) the number of blocks already allocated to all non-volatile memory devices associated with the block. Afterward, the block with the greatest amount of available memory is selected to store the sector of data.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 9, 1996
    Assignee: Intel Corporation
    Inventors: Steven Wells, Robert N. Hasbun, Sara Domonkos, Steven S. Barbarich
  • Patent number: 5479633
    Abstract: A method of initiating and controlling background clean-up of a solid state memory disk is described. Background clean-up begins by enabling a clean-up state machine after completion of a write command. Next, a next state pointer is set to an initial state for evaluating whether clean-up is necessary. Actual execution of background clean-up begins when the processing unit allocates execution time for clean-up. As each state is executed, the next state pointer is reset so that it points to the next clean-up state to be executed. States pointed to by the next state pointer are executed until a block of the solid state memory disk is cleaned-up.Also described is a method of automatically performing foreground clean-up of a solid state memory disk. A method of forcing clean-up is also described.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: December 26, 1995
    Assignee: Intel Corporation
    Inventors: Steven Wells, Robert N. Hasbun
  • Patent number: 5473753
    Abstract: A method for monitoring the operations of a flash memory array divided into individually erasable blocks of memory in order to assure the integrity of data stored in the array in which each read or write operation is verified to detect an error which may have occurred in the operation including the steps of attempting at least one retry operation whenever an error occurs to determine whether the error is repeatable, marking the block to indicate valid data should be removed from the block if the error is found to be repeatable, removing the valid information from the block if the error is found to be repeatable, and removing a block with a repeatable error from operation.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: December 5, 1995
    Assignee: Intel Corporation
    Inventors: Steven E. Wells, Eric J. Magnusson, Robert N. Hasbun
  • Patent number: 5471604
    Abstract: A method of allocating free physical memory in a solid state memory disk for a sector of data of a given size is described. Allocation begins by determining the amount of free physical memory in each block of the solid state memory disk. Afterward, the block with the greatest amount of free physical memory is selected. Sufficient free memory to store the sector of data is reserved in the selected block, provided the amount of free memory within selected block exceeds the given size of the sector of data.A method of allocating free physical memory for sectors of user data stored within a block that is the focus of clean-up is also described.A method of locating a sector of data stored in a solid state memory disk given a sector number and a pointer to a block sector translation table of a block is also described.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: November 28, 1995
    Assignee: Intel Corporation
    Inventors: Robert N. Hasbun, Stephen Wells