Patents by Inventor Robert Seidel

Robert Seidel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140308022
    Abstract: Some embodiments provide systems and/or methods of managing content in providing a playback experience associated with a portable storage medium by detecting access to a first portable storage medium with multimedia content recorded on the first portable storage medium; evaluating content on the first portable storage medium; evaluating local memory of the multimedia playback device; determining, in response to the evaluation of the content on the first portable storage medium and the evaluation of the local memory, whether memory on the local memory needs to be freed up in implementing playback of multimedia content in association with the first portable storage medium; and moving one or more contents stored on the local memory of the multimedia playback device to a virtual storage accessible by the multimedia playback device over a distributed network in response to determining that memory on the local memory needs to be freed up.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Inventors: Robert Seidel, Allan Lamkin
  • Publication number: 20140264758
    Abstract: One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Torsten Huisinga, Keith Donegan, Robert Seidel
  • Patent number: 8799395
    Abstract: Some embodiments provide systems and/or methods of managing content in providing a playback experience associated with a portable storage medium by detecting access to a first portable storage medium with multimedia content recorded on the first portable storage medium; evaluating content on the first portable storage medium; evaluating local memory of the multimedia playback device; determining, in response to the evaluation of the content on the first portable storage medium and the evaluation of the local memory, whether memory on the local memory needs to be freed up in implementing playback of multimedia content in association with the first portable storage medium; and moving one or more contents stored on the local memory of the multimedia playback device to a virtual storage accessible by the multimedia playback device over a distributed network in response to determining that memory on the local memory needs to be freed up.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: August 5, 2014
    Assignee: Deluxe Media Inc.
    Inventors: Robert Seidel, Allan Lamkin
  • Patent number: 8741770
    Abstract: Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: June 3, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Robert Seidel, Juergen Boemmels, Thomas Foltyn
  • Patent number: 8664657
    Abstract: A circuit is disclosed. The circuit includes at least one nanostructure and a carbon interconnect formed by a substantially carbon layer, wherein the nanostructure and the carbon interconnect are directly coupled to one another.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: March 4, 2014
    Assignee: Qimonda AG
    Inventors: Georg Duesberg, Franz Kreupl, Robert Seidel, Gernot Steinlesberger
  • Publication number: 20140058121
    Abstract: A light-oil separator device includes a collector funnel having a downwardly directed stem portion having an outside diameter. The stem portion adapts to insert in an upward extending neck portion of a collection vessel. The neck portion includes an inner diameter that is greater than the outer diameter of the funnel stem. The neck also includes an oil port at a first height. The vessel includes a body having a hydrosol port at a lower portion of a body sidewall. This port connects to an evacuation tube having a proximal end and an S-shape. This conduit includes an air vent at a top portion at a second height lower than the first height, the air vent extends upward to a height higher than the first height. The S-shape conduit terminates with a downward facing end portion at its distal end.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 27, 2014
    Inventor: Robert Seidel
  • Patent number: 8580684
    Abstract: In sophisticated semiconductor devices, contact elements in the contact level may be formed by patterning the contact openings and filling the contact openings with the metal of the first metallization layer in a common deposition sequence. To this end, in some illustrative embodiments, a sacrificial fill material may be provided in contact openings prior to depositing the dielectric material of the first metallization layer.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: November 12, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert Seidel, Kai Frohberg, Carsten Peters
  • Patent number: 8420533
    Abstract: In sophisticated metallization systems, vertical contacts and metal lines may be formed on the basis of a dual inlaid strategy, wherein an edge rounding or corner rounding may be applied to the trench hard mask prior to forming the via openings on the basis of a self-aligned via trench concept. Consequently, self-aligned interconnect structures may be obtained, while at the same time providing superior fill conditions during the deposition of barrier materials and conductive fill materials.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: April 16, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert Seidel, Thomas Werner
  • Patent number: 8389401
    Abstract: When forming contact levels of sophisticated semiconductor devices, a superior bottom to top fill behavior may be accomplished by applying an activation material selectively in the lower part of the contact openings and using a selective deposition technique. Consequently, deposition-related irregularities, such as voids, may be efficiently suppressed even for high aspect ratio contact openings.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: March 5, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Robert Seidel, Markus Nopper, Axel Preusse
  • Patent number: 8344474
    Abstract: In a sophisticated metallization system, self-aligned air gaps may be provided in a locally selective manner by using a radiation sensitive material for filling recesses or for forming therein the metal regions. Consequently, upon selectively exposing the radiation sensitive material, a selective removal of exposed or non-exposed portions may be accomplished, thereby resulting in a highly efficient overall manufacturing flow.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: January 1, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Seidel, Thomas Werner
  • Patent number: 8338314
    Abstract: In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: December 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Heike Salz, Robert Seidel
  • Patent number: 8319259
    Abstract: A semiconductor power switch and method is disclosed. In one Embodiment, the semiconductor power switch has a source contact, a drain contact, a semiconductor structure which is provided between the source contact and the drain contact, and a gate which can be used to control a current flow through the semiconductor structure between the source contact and the drain contact. The semiconductor structure has a plurality of nanowires which are connected in parallel and are arranged in such a manner that each nanowire forms an electrical connection between the source contact and the drain contact.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: November 27, 2012
    Assignee: Infineon Technologies AG
    Inventors: Franz Kreupl, Robert Seidel
  • Patent number: 8314494
    Abstract: A conductive cap material for a copper region may be provided with enhanced etch resistivity by taking into consideration the standard electrode potential of one or more of the species contained therein. For example, instead of a conventionally used CoWP alloy, a modified alloy may be used, by substituting the cobalt species by a metallic species having a less negative standard electrode potential, such as nickel. Consequently, device performance may be enhanced, while at the same time the overall process complexity may be reduced.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: November 20, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Markus Nopper, Axel Preusse, Robert Seidel
  • Patent number: 8293641
    Abstract: By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: October 23, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Seidel, Carsten Peters, Frank Feustel
  • Publication number: 20120220119
    Abstract: Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.
    Type: Application
    Filed: May 10, 2012
    Publication date: August 30, 2012
    Inventors: Ralf Richter, Robert Seidel, Juergen Boemmels, Thomas Foltyn
  • Patent number: 8198190
    Abstract: Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: June 12, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Robert Seidel, Juergen Boemmels, Thomas Foltyn
  • Publication number: 20120131125
    Abstract: Some embodiments provide systems and/or methods of managing content in providing a playback experience associated with a portable storage medium by detecting access to a first portable storage medium with multimedia content recorded on the first portable storage medium; evaluating content on the first portable storage medium; evaluating local memory of the multimedia playback device; determining, in response to the evaluation of the content on the first portable storage medium and the evaluation of the local memory, whether memory on the local memory needs to be freed up in implementing playback of multimedia content in association with the first portable storage medium; and moving one or more contents stored on the local memory of the multimedia playback device to a virtual storage accessible by the multimedia playback device over a distributed network in response to determining that memory on the local memory needs to be freed up.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 24, 2012
    Applicant: DELUXE DIGITAL STUDIOS, INC.
    Inventors: Robert Seidel, Allan Lamkin
  • Patent number: 8163594
    Abstract: In a semiconductor device, a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrical performance compared to doped semiconductor materials and the like. Thus, in some illustrative embodiments, the through hole vias may be formed prior to any process steps used for forming critical circuit elements, thereby substantially avoiding any interference of the through hole via structure with a device level of the corresponding semiconductor device. Consequently, highly efficient three-dimensional integration schemes may be realized.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: April 24, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert Seidel, Frank Feustel, Ralf Richter
  • Patent number: 8048796
    Abstract: In a sophisticated metallization system of a semiconductor device, air gaps may be formed in a self-aligned manner on the basis of a sacrificial material, such as a carbon material, which is deposited after the patterning of a dielectric material for forming therein a via opening. Consequently, superior process conditions during the patterning of the via opening and the sacrificial material in combination with a high degree of flexibility in selecting appropriate materials for the dielectric layer and the sacrificial layer may provide superior uniformity and device characteristics.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: November 1, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Robert Seidel, Thomas Werner
  • Patent number: 8039398
    Abstract: Prior to performing a CMP process for planarizing a metallization level of an advanced semiconductor device, an appropriate cap layer may be formed in order to delay the exposure of metal areas of reduced height level to the highly chemically reactive slurry material. Consequently, metal of increased height level may be polished with a high removal rate due to the mechanical and the chemical action of the slurry material, while the chemical interaction with the slurry material may be substantially avoided in areas of reduced height level. Therefore, a high process uniformity may be achieved even for pronounced initial surface topographies and slurry materials having a component of high chemical reactivity.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Feustel, Robert Seidel, Juergen Boemmels