Patents by Inventor Robert Seidel

Robert Seidel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7524681
    Abstract: The present invention relates to a method for determining the condition of a biological fluid by recording the IR spectrum of a sample of the biological fluid. To this end, the biological fluid can be examined in its native form. The method of the invention is usable, for example, for detecting pathological conditions in organisms.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: April 28, 2009
    Inventors: Andreas Wolf, Ralf Masuch, Robert Seidel
  • Patent number: 7525319
    Abstract: A method of electrically qualifying high speed printed circuit board (PCB) connectors includes mounting a PCB connector on a test card, sending bit patterns through a first portion of the test card, evaluating a waveform on a sense signal on a second portion of the test card for the bit patterns launched on said first portion of the test card to measure common mode noise, and comparing the measured common mode noise of the second portion of the test card to a golden standard performed on a pre-qualified connector. The first portion of the test card comprises connectors to inject bit patterns. The second portion of the test card includes a split plane which induces common mode noise on a sense signal, the sense signal, and a termination pack. If the measured common mode noise on the PCB connector is worse than the golden standard, then the PCB connector is disqualified. If the measured common mode noise on the PCB connector is as good as or better than the golden standard, then the PCB connector is qualified.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: April 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Rubina Firdaus Ahmed, Moises Cases, Bradley Donald Herrman, Kent Barclay Howieson, Bhyrav Murthy Mutnury, Pravin Patel, Peter Robert Seidel
  • Publication number: 20090087999
    Abstract: By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.
    Type: Application
    Filed: July 7, 2008
    Publication date: April 2, 2009
    Inventors: Ralf Richter, Robert Seidel, Carsten Peters
  • Publication number: 20080296557
    Abstract: A semiconductor power switch and method is disclosed. In one embodiment the semiconductor power switch has a source contact, a drain contact, a semiconductor structure which is provided between the source contact and the drain contact, and a gate which can be used to control a current flow through the semiconductor structure between the source contact and the drain contact. The semiconductor structure has a plurality of nanowires which are connected in parallel and are arranged in such a manner that each nanowire forms an electrical connection between the source contact and the drain contact.
    Type: Application
    Filed: January 19, 2005
    Publication date: December 4, 2008
    Inventors: Franz Kreupl, Robert Seidel
  • Publication number: 20080296559
    Abstract: A nanoelement field effect transistor includes a nanotube disposed on the substrate. A first source/drain region is coupled to a first end portion of the nanoelement and a second source/drain region is coupled to a second end portion of the nanoelement. A recess in a surface region of the substrate is arranged in such a manner that a region of the nanoelement arranged between the first and second end portions is taken out over the entire periphery of the nanoelement. A gate-insulating structure covers the periphery of the nanoelement and a gate structure covers the periphery of the gate-insulating structure.
    Type: Application
    Filed: August 12, 2008
    Publication date: December 4, 2008
    Inventors: Franz Kreupl, Robert Seidel
  • Publication number: 20080265426
    Abstract: A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A layer of a second material is formed over the layer of first material and the protection layer to fill the opening with the second material. A planarization process is performed to remove portions of the layer of second material outside the opening. At least a portion of the protection layer is not removed during the planarization process. An etching process is performed to remove the portions of the protection layer which were not removed during the planarization process.
    Type: Application
    Filed: November 21, 2007
    Publication date: October 30, 2008
    Inventors: Robert Seidel, Ralf Richter, Frank Feustel
  • Patent number: 7425487
    Abstract: The invention relates to a method for the production of a nanoelement field effect transistor, a nanoelement field effect transistor and a nanoelement arrangement. According to the method for the production of a nanoelement field effect transistor, a nanoelement is formed, a first and a second source-/drain area is coupled to the nanoelement, a surface area of a substrate is removed, such that a region of the nanoelement is exposed, and a gate-insulating structure and a gate structure are formed in a covered manner fully encompassing the nanoelement.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: September 16, 2008
    Assignee: Qimonda AG
    Inventors: Franz Kreupl, Robert Seidel
  • Publication number: 20080206994
    Abstract: Prior to performing a CMP process for planarizing a metallization level of an advanced semiconductor device, an appropriate cap layer may be formed in order to delay the exposure of metal areas of reduced height level to the highly chemically reactive slurry material. Consequently, metal of increased height level may be polished with a high removal rate due to the mechanical and the chemical action of the slurry material, while the chemical interaction with the slurry material may be substantially avoided in areas of reduced height level. Therefore, a high process uniformity may be achieved even for pronounced initial surface topographies and slurry materials having a component of high chemical reactivity.
    Type: Application
    Filed: October 3, 2007
    Publication date: August 28, 2008
    Inventors: Frank Feustel, Robert Seidel, Juergen Boemmels
  • Publication number: 20080182409
    Abstract: By forming an activation/nucleation layer selectively at a bottom of an opening, efficient electroless deposition techniques may be used for forming contacts, vias and trenches of advanced semiconductor devices. By selectively providing the activation material, a self-aligned bottom-to-top fill behavior may be obtained.
    Type: Application
    Filed: July 25, 2007
    Publication date: July 31, 2008
    Inventors: Robert Seidel, Axel Preusse, Ralf Richter
  • Publication number: 20080182406
    Abstract: By appropriately designing a plurality of deposition steps and intermediate sputter processes, the formation of a barrier material within a via opening may be accomplished on the basis of a highly efficient process strategy that readily integrates conductive cap layers formed above metal-containing regions into well-approved process sequences.
    Type: Application
    Filed: June 12, 2007
    Publication date: July 31, 2008
    Inventors: Axel Preusse, Michael Friedemann, Robert Seidel, Berit Freudenberg
  • Patent number: 7326465
    Abstract: An integrated electronic component having a substrate, a metal multilayer system, which is arranged at least on regions of the substrate, and a nonconductive layer, which is arranged on the metal multilayer system and has at least one contact hole, in which at least one carbon nanotube is grown on the metal multilayer system at the bottom of the contact hole. The metal multilayer system includes a high-melting metal layer, a metal separating layer, a catalyst layer, and a final metal separating layer. The high-melting metal layer is composed of at least one of tantalum, molybdenum, and tungsten. The metal separating layer is composed of aluminum, gold, or silver. The catalyst layer is composed of at least one of iron, cobalt, nickel, yttrium, titanium, platinum, and palladium, and a combination thereof. The final metal separating layer, which is arranged above the catalyst layer, is composed of aluminum.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: February 5, 2008
    Assignee: Infineon Technologies AG
    Inventors: Robert Seidel, Franz Kreupl, Andrew Graham
  • Publication number: 20080003826
    Abstract: By additionally planarizing the surface topography of a planarization layer, which may be accomplished on the basis of mechanical contact, a uniform force, a polishing process and the like, an enhanced surface topography may be provided which may be advantageously used in subsequent patterning processes, such as photolithography, imprint techniques and the like.
    Type: Application
    Filed: February 14, 2007
    Publication date: January 3, 2008
    Inventors: Thomas Werner, Robert Seidel, Frank Feustel
  • Publication number: 20080003818
    Abstract: By forming metallization structures on the basis of an imprint technique, in which via openings and trenches may be commonly formed, a significant reduction of process complexity may be achieved due to the omission of at least one further alignment process as required in conventional process techniques. Furthermore, the flexibility and efficiency of imprint lithography may be increased by providing appropriately designed imprint molds in order to provide via openings and trenches exhibiting an increased fill capability, thereby also improving the performance of the finally obtained metallization structures with respect to reliability, resistance against electromigration and the like.
    Type: Application
    Filed: February 6, 2007
    Publication date: January 3, 2008
    Inventors: Robert Seidel, Carsten Peters, Frank Feustel
  • Publication number: 20060261419
    Abstract: The invention relates to a method for the production of a nanoelement field effect transistor, a nanoelement field effect transistor and a nanoelement arrangement. According to the method for the production of a nanoelement field effect transistor, a nanoelement is formed, a first and a second source-/drain area is coupled to the nanoelement, a surface area of a substrate is removed, such that a region of the nanoelement is exposed, and a gate-insulating structure and a gate structure are formed in a covered manner fully encompassing the nanoelement.
    Type: Application
    Filed: July 7, 2006
    Publication date: November 23, 2006
    Inventors: Franz Kreupl, Robert Seidel
  • Publication number: 20060234080
    Abstract: An integrated electronic component having a substrate, a metal multilayer system, which is arranged at least on regions of the substrate, and a nonconductive layer, which is arranged on the metal multilayer system and has at least one contact hole, in which at least one carbon nanotube is grown on the metal multilayer system at the bottom of the contact hole. The metal multilayer system includes a high-melting metal layer, a metal separating layer, a catalyst layer, and a final metal separating layer. The high-melting metal layer is composed of at least one of tantalum, molybdenum, and tungsten. The metal separating layer is composed of aluminum, gold, or silver. The catalyst layer is composed of at least one of iron, cobalt, nickel, yttrium, titanium, platinum, and palladium, and a combination thereof. The final metal separating layer, which is arranged above the catalyst layer, is composed of aluminum.
    Type: Application
    Filed: August 23, 2005
    Publication date: October 19, 2006
    Applicant: Infineon Technologies AG
    Inventors: Robert Seidel, Franz Kreupl, Andrew Graham
  • Publication number: 20040218705
    Abstract: A Clock and Data Recovery (CDR) system includes a phase rotator which shifts the phases of signals received from a phase lock loop (PLL) to generate signals for oversampling a serial data stream. The signals derived from oversampling are processed to capture data and generate control signals for adjusting the phase rotator.
    Type: Application
    Filed: January 30, 2004
    Publication date: November 4, 2004
    Applicant: International Business Machines Corporation
    Inventors: Hayden Clavie Cranford, Matthew Richard Cordrey-Gal, James Stephen Mason, Philip John Murfet, Gareth John Nicholls, Todd Morgan Rasmus, Martin Leo Schmatz, Peter Robert Seidel
  • Publication number: 20040092027
    Abstract: The present invention relates to a method for determining the condition of a biological fluid by recording the IR spectrum of a sample of the biological fluid. To this end, the biological fluid can be examined in its native form. The method of the invention is usable, for example, for detecting pathological conditions in organisms.
    Type: Application
    Filed: November 18, 2003
    Publication date: May 13, 2004
    Inventors: Andreas Wolf, Ralf Masuch, Robert Seidel
  • Patent number: 6245174
    Abstract: A dimensionally heat recoverable tubular article (1) is made by spirally wrapping cross-linked polymeric sheet (3) a number of times, and directly fusing together overlapping layers (5) of the cross-linked sheet (3) to form a consolidated tubular article. The final article has a wall thickness of at least 2.2 mm. Articles according to the invention may be made of different diameter and different wall thickness, starting from the same thickness initial sheet material, simply by changing the circumference of wrapping or the number of spiral wraps. Articles according to the invention are particularly useful as casings over joints between district heating pipes.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: June 12, 2001
    Inventors: Johannes Maria Cordia, Robert Seidel, Robert Ritter
  • Patent number: 5815480
    Abstract: A process for determining the Start Program Point for a compact disc recording of data first recorded on an other medium, by measuring with the aid of a microscope the radius of the transition from the first pit/land transition from silence to data, measuring with the aid of an editor for the other medium a delay period of silence intended to be part of the data, calculating the Start Program Point and recording the Start Program Point thus calculated on the compact disc.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: September 29, 1998
    Assignee: WEA Manufacturing, Inc.
    Inventor: Robert Seidel