Patents by Inventor Rohit Kumar

Rohit Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170244518
    Abstract: Methods and systems for intelligent network checksum processing are disclosed. A method for intelligent network checksum processing may include receiving a data unit at a receiver network element sent from a sender network element, determining a success count of the sender network element, determining whether to perform a checksum validation at the receiver network element, wherein the determining may include skipping the checksum validation if the success count of the sender network element is greater than the predefined threshold success count, and performing the checksum validation if the success count of the sender network element is not greater than a predefined threshold success count, incrementing the success count of the sender network element if the checksum validation is performed and the checksum validation is successful, and resetting the success count of the sender network element if the checksum validation is performed and the checksum validation is unsuccessful.
    Type: Application
    Filed: February 23, 2016
    Publication date: August 24, 2017
    Inventors: Ankit Singh, Rohit Kumar Arehalli
  • Publication number: 20170208443
    Abstract: A method of adaptively reporting buffer status by a dual subscriber identity module dual standby (DSDS) terminal is provided. The method includes computing a rate at which uplink (UL) grants are allocated by a network over a period of time for a first subscriber unit associated with the DSDS terminal, determining a first time period to initiate buffer status reporting (BSR) using a radio frequency (RF) unit, wherein the first time period corresponds to a time period in which a BSR interval initializes, determining a second time period in which a second subscriber unit associated with the DSDS terminal requires the RF unit, and adaptively reporting the buffer status based on the rate and a difference between the second time period and the first time period.
    Type: Application
    Filed: August 4, 2016
    Publication date: July 20, 2017
    Inventors: Ashish Kumar GUPTA, Balaji Srinivasan THIRUVENKATACHARI, Rohit KUMAR, Shrinath Ramamoorthy MADHURANTAKAM, Swapnil Vinod KHACHANE
  • Patent number: 9710463
    Abstract: A two-way speech-to-speech (S2S) translation system actively detects a wide variety of common error types and resolves them through user-friendly dialog with the user(s). Examples include features including one or more of detecting out-of-vocabulary (OOV) named entities and terms, sensing ambiguities, homophones, idioms, ill-formed input, etc. and interactive strategies for recovering from such errors. In some examples, different error types are prioritized and systems implementing the approach can include an extensible architecture for implementing these decisions.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: July 18, 2017
    Assignee: Raytheon BBN Technologies Corp.
    Inventors: Rohit Prasad, Rohit Kumar, Sankaranarayanan Ananthakrishnan, Sanjika Hewavitharana, Matthew Roy, Frederick Choi
  • Publication number: 20170168839
    Abstract: The description covers a system and method for operating a micro-processing system having a runahead mode of operation. In one implementation, the method includes providing, for a first portion of code, a runahead correlate. When the first portion of code is encountered by the micro-processing system, a determination is made as to whether the system is operating in the runahead mode. If so, the system branches to the runahead correlate, which is specifically configured to identify and resolve latency events likely to occur when the first portion of code is encountered outside of runahead. Branching out of the first portion of code may also be performed based on a determination that a register is poisoned.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 15, 2017
    Inventors: Rohit Kumar, Guillermo Rozas, Magnus Ekman, Lawrence Spracklen
  • Publication number: 20170165655
    Abstract: A novel pt/pd sodalite caged catalyst combination with sulfided base metal catalyst for improved catalytic hydroprocessing of renewable feedstock. Particularly, the invention relates to a process for preparation of the said catalyst. More particularly, the invention relates to a process for the preparation of hydrocarbon fuel from the feed stock using a said catalyst. Further, the invention discloses a novel catalyst and a process for the preparation of the Pt/Pd encapsulated in sodalite cage with silica-alumina ZSM-5 synthesized around it supported with nickel, molybdenum, cobalt, tungsten or one or more thereof. The invention also provides process to convert vegetable oils, free fatty acids, and microbial lipids, bio-crude and conventional non-renewable crude based feed stocks such as diesel, naphtha, kerosene, gas oil, residue, etc.
    Type: Application
    Filed: October 18, 2016
    Publication date: June 15, 2017
    Applicant: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH
    Inventors: Anil Kumar SINHA, Mohit ANAND, Saleem Akthar FAROOQUI, Rakesh KUMAR, Rakesh Kumar JOSHI, Rohit KUMAR, Tasleem KHAN, Parvez ALAM, Gopalan Sibi MALAYIL
  • Publication number: 20170171148
    Abstract: A network device may be configured to cause one or more network address allocation communications broadcast in a network to be communicated as directed unicast communications. More particularly, in a Local Area Network, a routing device such as a switch may be modified to receive broadcast communications for network address allocation, and instead of propagating the broadcast communications as broadcast communications, the routing device may route the network address allocation communications as directed unicast communications in the Local Area Network.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 15, 2017
    Inventors: Ankit Singh, Rohit Kumar Arehalli, Shekar Babu Suryananarayana
  • Publication number: 20170160791
    Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.
    Type: Application
    Filed: February 15, 2017
    Publication date: June 8, 2017
    Inventors: John H. Mylius, Conrad H. Ziesler, Daniel C. Murray, Jong-Suk Lee, Rohit Kumar
  • Patent number: 9672305
    Abstract: A method for designing clock gates which may reduce timing requirements associated with clock gating control signals may include identifying a clock gating function included in a Hardware Description Language of an integrated circuit, wherein the clock gating function may include capturing a state of an enable signal dependent upon a clock signal. The method may include determining a delay time for capturing the state of the enable signal dependent on a time difference between transitions of the enable signal and the clock signal. The method may include creating a gating circuit, in which the gating circuit includes a delay unit coupled to a source of the clock signal, and wherein a delay value is dependent upon the amount of time to delay capturing the enable signal. The method may include modifying the HDL model dependent upon the clock gating circuit.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: June 6, 2017
    Assignee: Apple Inc.
    Inventors: Suparn Vats, Daniel J. Flees, Rohit Kumar
  • Patent number: 9612663
    Abstract: A device and a method facilitating generation of one or more intuitive gesture sets for the interpretation of a specific purpose are disclosed. Data is captured in a scalar and a vector form which is further fused and stored. The intuitive gesture sets generated after the fusion are further used by one or more components/devices/modules for one or more specific purpose. Also incorporated is a system for playing a game. The system receives one or more actions in a scalar and a vector from one or more user in order to map the action with at least one pre stored gesture to identify a user in control amongst a plurality of users and interpret the action of user for playing the game. In accordance with the interpretation, an act is generated by the one or more component of the system for playing the game.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 4, 2017
    Assignee: Tata Consultancy Services Limited
    Inventors: Aniruddha Sinha, Kingshuk Chakravarty, Rohit Kumar Gupta, Arpan Pal, Anupam Basu
  • Patent number: 9606605
    Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: March 28, 2017
    Assignee: Apple Inc.
    Inventors: John H. Mylius, Conrad H. Ziesler, Daniel C. Murray, Jong-Suk Lee, Rohit Kumar
  • Patent number: 9582280
    Abstract: The description covers a system and method for operating a micro-processing system having a runahead mode of operation. In one implementation, the method includes providing, for a first portion of code, a runahead correlate. When the first portion of code is encountered by the micro-processing system, a determination is made as to whether the system is operating in the runahead mode. If so, the system branches to the runahead correlate, which is specifically configured to identify and resolve latency events likely to occur when the first portion of code is encountered outside of runahead. Branching out of the first portion of code may also be performed based on a determination that a register is poisoned.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: February 28, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Rohit Kumar, Guillermo Rozas, Magnus Ekman, Lawrence Spracklen
  • Publication number: 20170048304
    Abstract: A pre-boot file transfer system includes at least one server device that creates a plurality of packets for a file and provides a respective file offset value for each of the plurality of packets in a header of that packet. The at least one server device transmits each of the plurality of packets over a network to a client device that is in a pre-boot environment. The client device receives each of the plurality of packets and stores the plurality of packets in a receive buffer in the order that the plurality of packets were received. The client device then writes the plurality of packets that were stored in the receive buffer into an application buffer in an order that is defined by the respective file offset values for the plurality of packets.
    Type: Application
    Filed: August 11, 2015
    Publication date: February 16, 2017
    Inventors: Ankit Singh, Shekar Babu Suryanarayana, Rohit Kumar Arehalli
  • Patent number: 9570252
    Abstract: A system for operating an on-load tap changer (OLTC) includes a plurality of legs that include mechanical switches. At least one leg switches from a first to a second tap of the OLTC on receipt of a tap change signal. At least one mechanical switch is activated to establish an electrical connection between one of the first and the second tap and a power terminal of the OLTC. Further, the system includes semiconductor switches that are parallel to the mechanical switches and when activated electrically couple one of the first and the second tap and the power terminal. The system includes a processing unit that selectively activates and deactivates the mechanical and semiconductor switches in such a way that electrical contact is maintained between at least one of the taps and the power terminal during the transition of at least one leg from the first tap to the second tap.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: February 14, 2017
    Assignee: General Electric Company
    Inventors: Piniwan Thiwanka Bandara Wijekoon, Eva-Maria Baerthlein, Simon Herbert Schramm, Stefan Schroeder, Ara Panosyan, Rohit Kumar Gupta
  • Publication number: 20170039299
    Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.
    Type: Application
    Filed: August 6, 2015
    Publication date: February 9, 2017
    Inventors: Harsha Krishnamurthy, Mridul Agarwal, Shyam Sundar Balasubramanian, Christopher S. Thomas, Rajat Goel, Rohit Kumar, Muthukumaravelu Velayoudame
  • Patent number: 9565546
    Abstract: Various methods, apparatus, and computer readable media are disclosed for enhanced system acquisition while a user equipment (UE) is roaming. The UE may detect roaming from a coverage area associated with a first public land mobile network (PLMN) supporting hybrid voice and data to a coverage area associated with a second PLMN without support for hybrid voice and data. In response to the detection, the UE may store data corresponding to the second PLMN such that the second PLMN is a registered PLMN (RPLMN). The UE may initiate system acquisition, wherein the system acquisition includes searching for the RPLMN prior to searching for any other PLMN. The other PLMN may include a home PLMN (HPLMN). The coverage area associated with the first PLMN may be within a first country, and the coverage area associated with the second network may be within a second country different from the first country.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: February 7, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Mahesh Devdatta Telang, Ameya Rajendraprasad Kasbekar, Rohit Kumar Maharana
  • Publication number: 20170034781
    Abstract: A User Equipment (UE) and a method for enhancing uplink transmission handling in Discontinuous Reception (DRX) mode of the UE are provided. The method includes of receiving, by the UE, an uplink data transmission request in the DRX mode; computing a first transition time and a first Scheduling Request (SR) transition time; calculating a second transition time; determining if the second transition time is less than a third transition time; computing a wakeup transition time, if the second transition time is not less than the third transition time; and enhancing uplink transmission time by triggering a wakeup procedure for the UE at a fourth transition time.
    Type: Application
    Filed: September 9, 2015
    Publication date: February 2, 2017
    Inventors: Rohit KUMAR, Swapnil Vinod KHACHANE
  • Patent number: 9557754
    Abstract: A method of switching taps of an on-load tap changer includes providing a main finger, a first side finger including a first solid state switch and a second side finger including a second solid state switch. The main finger, the first side finger and the second side finger are utilized to provide a connection between the taps and a power terminal of the on-load tap changer. The method also includes triggering the on-load tap changer to shift the fingers from a first tap to a second tap of the on-load tap changer when a tap change signal is received and utilizing the first solid state switch and the second solid state switch to commutate a current during the tap change operation.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 31, 2017
    Assignee: General Electric Company
    Inventors: Ara Panosyan, Eva-Maria Baerthlein, Simon Herbert Schramm, Stefan Schroeder, Rohit Kumar Gupta, Pinwan Thiwanka Bandara Wijekoon, Malcolm Graham Smith, Jr.
  • Patent number: 9454196
    Abstract: In some embodiments, a system may include at least one voltage controller. At least one of the voltage controllers may assess, during use, an occurrence of a predetermined condition. In some embodiments, the system may include an at least first capacitor. The at least first capacitor may be coupled to at least one of the voltage controllers such that at least one of the voltage controllers engages the at least first capacitor to supply additional current when the predetermined condition occurs. When the increase in current is no longer required the at least first capacitor may be disengaged. The at least first capacitor may be charged when disengaged until a predetermined capacity.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: September 27, 2016
    Assignee: Apple Inc.
    Inventors: Matthias Knoth, Rohit Kumar, Eric Smith, Louis Luh
  • Publication number: 20160262004
    Abstract: Various methods, apparatus, and computer readable media are disclosed for enhanced system acquisition while a user equipment (UE) is roaming. The UE may detect roaming from a coverage area associated with a first public land mobile network (PLMN) supporting hybrid voice and data to a coverage area associated with a second PLMN without support for hybrid voice and data. In response to the detection, the UE may store data corresponding to the second PLMN such that the second PLMN is a registered PLMN (RPLMN). The UE may initiate system acquisition, wherein the system acquisition includes searching for the RPLMN prior to searching for any other PLMN. The other PLMN may include a home PLMN (HPLMN). The coverage area associated with the first PLMN may be within a first country, and the coverage area associated with the second network may be within a second country different from the first country.
    Type: Application
    Filed: June 30, 2015
    Publication date: September 8, 2016
    Inventors: Mahesh Devdatta Telang, Ameya Rajendraprasad Kasbekar, Rohit Kumar Maharana
  • Patent number: 9430608
    Abstract: Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with hold-time violations are wired later, thus fixing hold-time violations without scaling or adding further buffers. Hold times are re-evaluated once wiring of track routes is complete.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: August 30, 2016
    Assignee: Synopsys, Inc.
    Inventors: Karthik Ramaseshan Kalpat, Rohit Kumar, Narendra Nimmagadda, Saumil Sanjay Shah, Hsiao-Ping Tseng