Abstract: Systems and methods are provided for processing a payload portion of a received signal in a single carrier mode or a multiple carrier mode based on a portion of the received signal. A single carrier signaling portion is received at a first rate, and whether the payload portion of the signal is a single carrier signal or a multiple carrier signal is detected from the received single carrier signaling portion. The payload portion of the received signal is received at the first rate and demodulated in a single carrier mode if the detecting determines that the payload portion of the received signal is a single carrier signal, and the payload portion of the received signal is demodulated in a multiple carrier mode if the detecting determines that the payload portion of the received signal is a multiple carrier signal.

Abstract: A computer device (2010) with a file system having clusters and meta data. The computer device (2010) includes a processor (1030) and a storage (1025) coupled to the processor and having physical representations of instructions so that the processor is operable to reserve (230) at least one of the clusters and to create a log record when meta data for the file system is to be updated by a write (240) of such meta data beforehand to such a reserved cluster, and then set (250) at least one state entry to substantially represent readiness to write the meta data to the file system.

Abstract: Access to a privileged account is managed by first requiring authentication of a user logging into the account and then performing a policy evaluation to determine whether the identified user is allowed to log in using the privileged identity. Preferably, the authentication is a two factor authentication. The policy evaluation preferably enforces a policy, such as a role-based access control, and a context-based access control, a combination of such access controls, or the like. Thus, according to this approach, the entity is provided access to the privileged account if the user's identity is verified and a policy is met. In the alternative, the entity is denied access to the privileged account if either the authentication fails, or (assuming authentication does not fail) policy criteria for the user is not met.

Abstract: Flour may be treated to denature the proteins and modify starches. The invention includes methods and systems for determining whether to use treated flour or untreated flour. The invention also includes methods and systems for determining whether to treat flour or not.

Abstract: Systems, apparatuses, and techniques relating to wireless local area network devices are described. A described technique includes transmitting a sounding packet to a wireless communication device(s) to determine characteristics of spatial wireless channels, the sounding packet being based on a spatial mapping matrix; receiving a feedback packet(s) from the device(s), the feedback packet(s) being indicative of one or more feedback matrices, the one or more feedback matrices being derived from wireless channel estimations that are based on received versions of the sounding packet; generating spatially steered data packets based on multiple data streams and one or more steering matrices, which are based on the spatial mapping matrix and the one or more feedback matrices; and transmitting a frame that includes the spatially steered data packets to the device(s).

Abstract: Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.

Abstract: A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver ?(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver ?(i) is generated based at least in part on the first and second intermediate interleaver permutations.

Abstract: Techniques are disclosed relating to integrated circuits that implement a virtual memory. In one embodiment, an integrated circuit is disclosed that includes a translation lookaside buffer configured to store non-prefetched translations and a translation table configured to store prefetched translations. In such an embodiment, the translation lookaside buffer and the translation table share table walk circuitry. In some embodiments, the table walk circuitry is configured to store a translation in the translation table in response to a prefetch request and without updating the translation lookaside buffer. In some embodiments, the translation lookaside buffer, the translation table, and table walk circuitry are included within a memory management unit configured to service memory requests received from a plurality of client circuits via a plurality of direct memory access (DMA) channels.

Abstract: Techniques are provided for seamless integration of wired and wireless functionality packet forwarding in network. A plurality of access switches are provided in each of a plurality of mobility sub-domains that are part of a mobility domain of a network. Each access switch serves one or more Internet Protocol (IP) subnets, each comprising a plurality of IP addresses. An access switch obtains an IP address for a wireless device according to the one or more IP subnets that the access switch serves. The access switch sends an association advertisement message to indicate the IP address of the wireless device and to enable other access switches and routers to compute a path to the wireless device. When a wireless device obtains an IP address, it can keep the same IP address as it roams in the mobility domain.

Abstract: Embodiments of the invention provide an innovative, fully-automated system that facilitates the buying and selling of debt-based derivatives and other assets. The techniques described herein eliminate opaqueness, inefficiencies, and lack of risk monitoring and provide an end-to-end, highly efficient reverse-auction platform that considers many aspects of risk control and other parameters. This is accomplished while computing a true CDS price by incorporating reference entity, primary and secondary insurance company default risks. Furthermore, the reference entity pricing model decouples the borrower from the entity issuing the debt and eliminates rating inflation due to digital discontinuity.

Abstract: An Internet system for and method of automatic optimizing quantitative business objectives of sellers (advertisers) with synergistic pricing, promotions and advertisements, while simultaneously minimizing expenditure and discovery and optimizing allocation of advertising channels that optimize such objectives.

Abstract: Structures and methods for implementing alternating power gating in integrated circuits. A semiconductor structure includes a power gated circuit including a group of power gate switches and an alternating enable generator that generates enabling signals. Each respective one of the power gate switches is enabled by a respective one of the enabling signals. The alternating generator generates the enabling signals such that a first enabled power gate switch is alternated amongst the group of power gate switches.

Abstract: Systems and methods provide acceleration of automatic test pattern generation in a multi-core computing environment via multi-level parameter value optimization for a parameter set with speculative scheduling. The methods described herein use multi-core based parallel runs to parallelize sequential execution, speculative software execution to explore possible parameter sets, and terminate/prune runs when the optimum parameter value is found at a previous level. The present invention evaluates the design prior to the implementation of the compression IP so that it can define the configuration of DFT and ATPG to maximize the results of compression as measured by test data volume and test application time.

Abstract: Aspects of the invention provide an electrostatic discharge (ESD) protection device with reduced current leakage, and a related method. In one embodiment, an ESD protection device for an integrated circuit (IC) is provided. The ESD protection device includes: a resistor-capacitor (RC) timing circuit for selectively turning on the ESD protection device during an ESD event; a trigger circuit for receiving an output of the RC timing circuit and generating a trigger pulse for driving at least one of: a first ESD clamp and a second ESD clamp; and a selection circuit for selecting one of: the trigger circuit or a charge pump for controlling the second ESD clamp.

Abstract: A method for using a flexible size radio link control (RLC) protocol data unit (PDU) on an uplink is described. A request for an RLC PDU is received from a medium access control (MAC) layer. Radio conditions for a first uplink carrier and a second uplink carrier are determined. A size of the RLC PDU is selected based on the radio conditions. The RLC PDU is generated. The RLC PDU is sent to the MAC layer.

Abstract: A semiconductor device structure is embedded within a semiconductor chip that calibrates a photon-emission luminosity scale by running multiple known currents through the device. The method comprises embedding at least one photon emission device in an integrated circuit having at least one functional device. A control current is applied to the at least one photon emission device. The photon emission intensity produced by the at least one photon emission device is captured. The current density of the at least one photon emission device is calculated. A test current is applied to the at least one functional device. The photon emission intensity produced by the at least one functional device is captured. The current density of the at least one functional device is estimated based on a comparison with the calculated current density of the at least one photon emission device.

Abstract: Power flow controllers based on Imputed DC Link (IDCL) cells are provided. The IDCL cell is a self-contained power electronic building block (PEBB). The IDCL cell may be stacked in series and parallel to achieve power flow control at higher voltage and current levels. Each IDCL cell may comprise a gate drive, a voltage sharing module, and a thermal management component in order to facilitate easy integration of the cell into a variety of applications. By providing direct AC conversion, the IDCL cell based AC/AC converters reduce device count, eliminate the use of electrolytic capacitors that have life and reliability issues, and improve system efficiency compared with similarly rated back-to-back inverter system.

Abstract: The invention provides compounds of formula (I): or a salt thereof. The invention also provides pharmaceutical compositions comprising a compound of formula I, processes for preparing compounds of formula I, intermediates useful for preparing compounds of formula I and therapeutic methods using the compounds of formula I.

Abstract: A method and mechanism for reducing lock time of a dual-path phase lock loop (PLL). The PLL comprises a dual-path low-pass filter (LPF). The LPF includes a first filter and a second filter. The first filter comprises a passive second-order lead-lag low-pass filter. The second filter comprises a first-order lag low-pass filter. During a lock-acquisition state, an impedance value within the second stage is bypassed, which increases the loop bandwidth of the PLL. In addition, a resistance within the first stage is increased in order to increase the gain of the first stage and maintain stability within the PLL. During a lock state, the impedance value may no longer be bypassed and the increased resistance may be returned to its original value.

Abstract: This document discusses, among other things, a semiconductor device including a first metal layer coupled to a source region and a second metal layer coupled to a gate structure, wherein at least a portion of the first and second metal layers overlap vertically.