Patents by Inventor Roland Irsigler

Roland Irsigler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090072398
    Abstract: An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 19, 2009
    Applicant: Qimonda AG
    Inventors: Roland Irsigler, Harry Hedler, Stephan Dobritz
  • Publication number: 20080237891
    Abstract: A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Applicant: QIMONDA AG
    Inventors: Roland Irsigler, Steve Wood, Hermann Ruckerbauer, Richard Johannes Luyken, Carsten Niepelt
  • Publication number: 20080164611
    Abstract: An integrated circuit and a method for making an integrated circuit is disclosed. In one embodiment, at least one contact of an electrically conductive material is formed on a substrate. A layer is disposed on the substrate to a predetermined height of the contact. An electrically conductive via hole is provided in the layer by the contact.
    Type: Application
    Filed: March 14, 2007
    Publication date: July 10, 2008
    Applicant: QIMONDA AG
    Inventors: Harry Hedler, Franz Kreupl, Roland Irsigler
  • Publication number: 20080150154
    Abstract: A method for fabricating a circuit arrangement is provided. One embodiment provides a base layer, whereby the first layer is disposed on the base layer having at least one channel, whereby the first layer is fabricated from an electrically isolating material, whereby the base layer at least partially covers the channel, whereby a second layer is disposed on the first layer, the second layer comprising a recess, the second layer at least partially covering the channel and whereby the recess is at least partially arranged over the channel, whereby the channel and the recess are filled with a liquid, the liquid being cured and an electrical conductor being formed in the channel and in the recess.
    Type: Application
    Filed: January 16, 2007
    Publication date: June 26, 2008
    Applicant: QIMONDA AG
    Inventors: Harry Hedler, Roland Irsigler
  • Publication number: 20080099925
    Abstract: A method of forming flip chip bumps includes forming a plurality of metallization pads on a die. In another step, a structured layer having pores is formed on the die and metallization pads where the pads on the die are exposed through the pores. In yet another step, the die is transferred to a chamber having a liquid metal bath. In another step, a first pressure is created within the chamber followed by dipping the die in the liquid metal bath. In another step, a second pressure is created within the chamber such that liquid metal fills portions of the pores thereby forming metal pillars connected to the pads.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 1, 2008
    Applicant: QIMONDA AG
    Inventors: Roland Irsigler, Harry Hedler
  • Patent number: 7338843
    Abstract: A method for producing an electronic component, especially a memory chip, using a laser-induced correction to equalize an integrated circuit by means of at least one laser via in a layer at least partially covering the circuit. The component comprises a rewiring of the contact pads. The inventive method comprises the following steps: each laser via is closed by means of a separate covering layer which is to be applied locally; a rewiring extending between the local covering layers is created; the local covering layers are removed; and the laser-induced correction is carried out by means of the open laser vias.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: March 4, 2008
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Barbara Vasquez
  • Publication number: 20080029849
    Abstract: A method for placing material onto a target board by means of a transfer board comprising a plurality of blind holes, the method comprising the steps of immersing the transfer board in a material bath, wherein a first pressure acts on the material bath and a second pressure acts in the blind holes, and wherein the first pressure and the second pressure are substantially equal; generating a pressure difference between the first pressure and the second pressure, so that the blind holes of the transfer board are filled at least partially with the liquid material; extracting the transfer board from the material bath; and positioning the transfer board opposite to the target board, the material being expelled from the blind holes, such that the material touches the target board.
    Type: Application
    Filed: August 1, 2006
    Publication date: February 7, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Harry Hedler, Roland Irsigler, Judith Lehmann
  • Publication number: 20070273011
    Abstract: A method for fabricating a module having an electrical contact-connection is disclosed. One embodiment provides a chip having a contact area, applying a contact elevation to the contact area and applying a solder material to the contact elevation. The contact elevation may be applied to the contact area by using a bonding process in order to implement the contact elevation in the form of a stud bump.
    Type: Application
    Filed: May 23, 2007
    Publication date: November 29, 2007
    Applicant: QIMONDA AG
    Inventors: Laurence Singleton, Harry Hedler, Roland Irsigler
  • Patent number: 7265451
    Abstract: A semiconductor device comprises at least one first semiconductor component being located in a first plane and comprising an active area which has a first contact region and at least one second semiconductor component being located in a second plane and comprising a second active area which has a second contact region. The second semiconductor component is located at a distance vertically to the first semiconductor component and is orientated relative to the first semiconductor component, so that the first active area faces away from the second semiconductor component and the second active area faces away from the first semiconductor component. An adhesive layer is arranged between the first and the second semiconductor components and a frame region adjoins laterally the first semiconductor component and the second semiconductor component on at least one side. The frame region comprises a first surface and a second surface which is located opposite to the second surface.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: September 4, 2007
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler
  • Patent number: 7247948
    Abstract: A semiconductor device has a semiconductor substrate, at least a first and second rewiring device on a first surface of the semiconductor substrate for the provision of an electrical contact-connection of the semiconductor substrate, and a tapering, continuous opening from a first surface to a second, opposite surface of the semiconductor substrate. At least a third and fourth rewiring device is disposed on the second surface of the semiconductor substrate and a patterned metallization on the side areas of the opening for the separate contact-connection of the first and at least the second rewiring device.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: July 24, 2007
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Publication number: 20070120268
    Abstract: An electronic component includes a substrate having contacts and a chip having contacts and a passivation layer disposed on an active side of the chip. The active side of the chip is mounted on a first surface of the substrate by flip chip technology such that the contacts of the chip are electrically connected to the contacts of the substrate by means of connecting elements. Elastic elevations are disposed between the contacts of the chip and the contacts of the substrate and an underfiller is disposed in an intermediate space between the chip and the substrate and between the elastic elevations. The underfiller and the elastic elevations have substantially the same modulus of elasticity.
    Type: Application
    Filed: January 13, 2006
    Publication date: May 31, 2007
    Inventors: Roland Irsigler, Harry Hedler, Bernd Goller, Gerald Ofner
  • Patent number: 7211472
    Abstract: A method for producing a multi-chip module having application of at least one contact elevation onto a substrate, application and patterning of a rewiring device onto the substrate and the at least one contact elevation with provision of a contact device on the at least one contact elevation, application of a semiconductor chip onto the substrate with electrical contact-connection of the rewiring device; application of an encapsulating device that is not electrically conductive onto the semiconductor chip, the substrate, the rewiring device and the at least one contact elevation, the contact device on the at least one contact elevation at least touching a first surface of the encapsulating device; and repetition at least once of at least the first two steps, the first surface of the encapsulating device serving as a substrate and the correspondingly produced rewiring device making electrical contact with the contact device of the at least one contact elevation of the underlying plane.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: May 1, 2007
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler
  • Patent number: 7211451
    Abstract: A process for producing a component module comprising a module carrier and a plurality of components with which contact is made on the latter, comprising the following steps: arranging separated components on a surface-adhesive film at a predefined contact-specific spacing from one another, embedding the components in a flexible material in order to form a flexible holding frame which holds the components, pulling off the film, producing contact-making elements on the exposed side of the components, performing a functional test of the components and, if necessary, repair and/or replacement of components, and fixing and making contact with the components held in the holding frame on the module carrier.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: May 1, 2007
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Gerd Frankowsky, Harry Hedler, Barbara Vasquez, Roland Irsigler
  • Publication number: 20070084944
    Abstract: Method and apparatus for aligning components of a device. In one embodiment a method of aligning includes providing a device having a surface on which a number of adjusting structures is provided in predetermined regions, wherein each of the adjusting structures of the device has a first region having a first wettability and a second region having a second wettability, wherein the second wettability is lower than the first wettability. A number of liquid droplets is provided in a fixed arrangement which corresponds to the arrangement of the adjusting structures in the predetermined regions of the device. The device is placed on the liquid droplets in such a way that each of the droplets abuts at least partially on the inner region of the corresponding adjusting structure of the device in such a way that the device is aligned with regard to the arrangement of the number of droplets.
    Type: Application
    Filed: October 14, 2005
    Publication date: April 19, 2007
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Publication number: 20070032059
    Abstract: A method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure This invention provides a method of manufacturing a semiconductor structure having a wafer through-contact and a corresponding semiconductor structure.
    Type: Application
    Filed: August 2, 2005
    Publication date: February 8, 2007
    Inventors: Harry Hedler, Roland Irsigler
  • Publication number: 20070023886
    Abstract: The present invention relates to a method and apparatus for producing a chip arrangement. In one embodiment, the method includes providing a first chip having an electrically operable structure, of providing at least one through-via through the first chip, and of arranging at least one bond wire through the through-via in the first chip.
    Type: Application
    Filed: July 5, 2006
    Publication date: February 1, 2007
    Inventors: Harry Hedler, Roland Irsigler
  • Publication number: 20060244109
    Abstract: A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 2, 2006
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer, Barbara Vasquez
  • Publication number: 20060177964
    Abstract: The present invention provides a semiconductor module having: a semiconductor device (10) having a contact device (11) for making electrical contact with a connection device (17; 20) via a rewiring device (15, 15?, 15?); and a carrier device (12, 13, 14) for mechanically coupling the semiconductor device (10) to a connection device (17), the carrier device (12, 13, 14) having a gradient between a first modulus of elasticity at the semiconductor device (10) and a second, higher modulus of elasticity at the connection device (17; 20). The present invention likewise provides a method for producing a semiconductor module.
    Type: Application
    Filed: February 28, 2006
    Publication date: August 10, 2006
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer
  • Patent number: 7087512
    Abstract: A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: August 8, 2006
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer, Barbara Vasquez
  • Patent number: 7080988
    Abstract: The present invention relates to an elastic contact-connecting device. An elastic elevation 3 is applied to a carrier area 2 of a carrier 1. The elastic elevation 3 has a first oblique area 4, a second ramp 5 and a roof area 6. The first oblique area 4 has a lesser inclination (30) with regard to the carrier area 2 than the second oblique area 5. A contact region 20 is applied to the roof area 6 of the elastic elevation. The contact region 20 is connected to other structures 12 on the carrier 1 via a conductor track 10. For this purpose, the conductor track 10 is guided over the first oblique area 4. If a mating contact is pressed onto the contact region 20, the elastic elevation yields, but presses against the mating contact on account of its elastic property and thus enables a reliable contact. In this case, essentially only the second oblique area 5 is deformed; the first oblique area 4 and the conductor track 10 applied thereto are not subjected to any mechanical stress.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: July 25, 2006
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Roland Irsigler, Thorsten Meyer, Andreas Wolter