Patents by Inventor Roman A. Pletka

Roman A. Pletka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200057814
    Abstract: Techniques for selecting a storage node of a storage system to store data include applying a first function to at least some data chunks of an extent to provide respective first values for each of the at least some data chunks. A storage node, included within multiple storage nodes of a storage system, is selected to store the extent based on a majority vote derived from the respective first values.
    Type: Application
    Filed: November 28, 2017
    Publication date: February 20, 2020
    Inventors: NIKOLAS IOANNOU, IOANNIS KOLTSIDAS, ROMAN A. PLETKA, CHENG-CHUNG SONG, RADU STOICA, SASA TOMIC, ANDREW D. WALLS
  • Publication number: 20200057702
    Abstract: In a data storage system including a non-volatile random access memory (NVRAM) array, a page is a smallest granularity of the NVRAM array that can be accessed by read and write operations, and a memory block containing multiple pages is a smallest granularity of the NVRAM array that can be erased. Data are stored in the NVRAM array in page stripes distributed across multiple memory blocks. In response to detection of an error in a particular page of a particular block of the NVRAM array, only the particular page of the particular block is retired, such that at least two of the multiple memory blocks across which a particular one of the page stripes is distributed include differing numbers of active (non-retired) pages.
    Type: Application
    Filed: November 28, 2017
    Publication date: February 20, 2020
    Inventors: CHARLES J. CAMP, IOANNIS KOLTSIDAS, ROMAN A. PLETKA, ANDREW D. WALLS
  • Publication number: 20200051621
    Abstract: Performing a calibration of a NAND flash memory block that is in an open state. An open state of the NAND flash memory block is detected, the NAND flash memory block comprising a plurality of memory pages, each of which comprising a plurality of memory cells. A group of pages of the NAND flash memory block being in an open state having comparable characteristics is identified. A calibration of read voltage values to pages of the group of identified pages is performed.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 13, 2020
    Inventors: Nikolaos Papandreou, Roman A. Pletka, Sasa Tomic, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy Fisher
  • Patent number: 10552243
    Abstract: Technology for handling page size mismatches when DPL-CLR is performed at multiple levels of a data storage system (for example, RAID level and flash card level). A “corrective DPL” corrects only a portion of the data that would make up a page at the level at which the data is stored (that is, the “initial DPL level”), and, after that, a partially corrected page of data is formed and stored in data storage, with the partially corrected page: (i) having a page size characteristic of the initial DPL; (ii) including the part of the data corrected by the corrective DPL; and (iii) further including other data. In some embodiments, the other data has a pattern that indicates that it is invalid, erroneous data, such that an error message will be returned if this portion of the data is attempted to be read.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Roman A. Pletka, Timothy J. Fisher, Robert E. Galbraith, Kevin E. Sallese, Christopher M. Dennett
  • Patent number: 10552288
    Abstract: A data storage system includes a controller that controls a non-volatile memory array including a plurality of garbage collection units of physical memory. For each of the plurality of garbage collections units storing valid data, the controller determines an invalidation metric and a health-based adjustment of the invalidation metric. The controller selects a garbage collection unit on which to perform garbage collection from among a plurality of garbage collections units predominately based on the invalidation metric for the garbage collection unit and also based on the health-based adjustment for the garbage collection unit. In response to selection of the garbage collection unit, the controller performing garbage collection for the garbage collection unit.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sasa Tomic, Roman A. Pletka
  • Patent number: 10552063
    Abstract: A controller of a non-volatile memory manages each of multiple disjoint sets of physical pages as a respective page group. The controller mitigates errors by repetitively performing background mitigation reads of each of the plurality of blocks including, in order, performing a background mitigation read of a first physical page in a first page group in a first block; prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a first page group in each other of the plurality of blocks; performing a background mitigation read of a first physical page in a second page group in the first block; and prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a second page group in each other of the plurality of blocks.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Sasa Tomic, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy Fisher
  • Patent number: 10528424
    Abstract: A computer-implemented method, according to one embodiment, includes: detecting at least one read of a logical page straddled across codewords, storing an indication of a number of detected reads of the straddled logical page, and relocating the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page. When relocated, the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Nikolas Ioannou, Thomas Parnell, Roman A. Pletka, Sasa Tomic
  • Publication number: 20190391746
    Abstract: A controller of a non-volatile memory manages each of multiple disjoint sets of physical pages as a respective page group. The controller mitigates errors by repetitively performing background mitigation reads of each of the plurality of blocks including, in order, performing a background mitigation read of a first physical page in a first page group in a first block; prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a first page group in each other of the plurality of blocks; performing a background mitigation read of a first physical page in a second page group in the first block; and prior to again performing a background mitigation read in the first block, performing a background mitigation read of a first physical page in a second page group in each other of the plurality of blocks.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Nikolaos Papandreou, Sasa Tomic, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis, Aaron D. Fry, Timothy Fisher
  • Publication number: 20190391877
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a write request at a storage system which includes more than one storage device, determining a storage location for data included in the write request, and determining a storage location for parity information corresponding to the data included in the write request. A first copy of the data included in the write request is sent to a first storage device which corresponds to the storage location for the data included in the write request. Moreover, a second copy of the data included in the write request is sent to a second storage device which corresponds to the storage location for the parity information. One or more instructions to compute the parity information via a decentralized communication link with the remaining storage devices are sent to the second storage device. The first storage device is different than the second storage device.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Radu I. Stoica, Roman A. Pletka, Ioannis Koltsidas, Nikolas Ioannou, Antonios K. Kourtis, Sasa Tomic, Charalampos Pozidis, Brent W. Yardley
  • Publication number: 20190391752
    Abstract: In at least one embodiment, a controller of a non-volatile memory having a plurality of blocks of physical memory estimates a current value of a block health metric of the particular block based on a previous value of the block health metric and a reference block wear curve. The controller assigns the particular block a health grade based on the estimated current value of the block health metric and performs data placement in the block in accordance with the assigned health grade. The controller may calibrate a set of read threshold voltages of the particular block prior to estimating the current value of the block health metric.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Roman A. Pletka, Sasa Tomic, Nikolaos Papandreou, Nikolas Ioannou, Aaron D. Fry, Timothy Fisher
  • Publication number: 20190361771
    Abstract: A computer-implemented method, according to one embodiment, includes: sequentially adding metadata information that has been extracted from a received write command to a metadata buffer, and adding parity information that has been extracted from the received write command to a parity buffer. The data corresponding to the received write command is also sent to memory. A determination is made as to whether an open segment in the memory which corresponds to the write command has been filled. In response to determining that the open segment has been filled, the parity buffer is updated with the metadata information included in the metadata buffer. Moreover, the metadata information is destaged from the metadata buffer and parity information is destaged from the parity buffer to a physical storage location in the memory.
    Type: Application
    Filed: July 10, 2019
    Publication date: November 28, 2019
    Inventors: Ioannis Koltsidas, Charles J. Camp, Nikolas Ioannou, Roman A. Pletka, Antonios K. Kourtis, Sasa Tomic, Radu I. Stoica, Christopher Dennett, Andrew D. Walls
  • Publication number: 20190361772
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving, at a storage drive, a portion of a write command. Metadata information is extracted from the received portion of the write command, and sequentially added to a metadata buffer. Parity information is extracted from the received portion of the write command, and adding to a parity buffer. The data in the received portion of the write command is stored in a memory in the storage drive. A determination is also made as to whether an open segment in the memory which corresponds to the received portion of the write command has been filled. In response to determining that the open segment has been filled, the parity buffer is updated with the metadata information included in the metadata buffer. The metadata information and parity information is also destaged from the respective buffers to a physical storage location in the memory.
    Type: Application
    Filed: July 10, 2019
    Publication date: November 28, 2019
    Inventors: Ioannis Koltsidas, Charles J. Camp, Nikolas Ioannou, Roman A. Pletka, Antonios K. Kourtis, Sasa Tomic, Radu I. Stoica, Christopher Dennett, Andrew D. Walls
  • Patent number: 10482032
    Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao Y. Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
  • Publication number: 20190348130
    Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages including at least a first page and a second page. A controller of the non-volatile memory determines a first calibration interval for a first read voltage threshold defining a bit value in the first page and a different second calibration interval for a second read voltage threshold defining a bit value in the second page. The second calibration interval has a shorter duration than the first calibration interval. The controller calibrates the first and second read voltage thresholds for the plurality of memory cells in the non-volatile memory based on the determined first and second calibration intervals.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 14, 2019
    Inventors: MATT REUTER, SASA TOMIC, NIKOLAOS PAPANDREOU, TIMOTHY FISHER, AARON D. FRY, ROMAN A. PLETKA, NIKOLAS IOANNOU, CHARALAMPOS POZIDIS
  • Publication number: 20190347013
    Abstract: A controller performs background reads of multiple physical pages of a selected physical block of a non-volatile memory. The controller detects asymmetric transient errors in a physical page among the multiple physical pages based on a bit error rate (BER) observed in the background read of the physical page. In response to detecting the asymmetric transient errors, the controller mitigates the detected asymmetric transient errors by relocating valid logical pages of data from the physical page to another physical block of the non-volatile memory and by retaining valid logical pages of data programmed into other physical pages of the selected physical block.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 14, 2019
    Inventors: ROMAN A. PLETKA, NIKOLAOS PAPANDREOU, SASA TOMIC, NIKOLAS IOANNOU, AARON D. FRY, TIMOTHY FISHER
  • Publication number: 20190340121
    Abstract: A controller of a non-volatile memory tracks identifiers of logical erase blocks (LEBs) for which programming has closed. A first subset of the closed LEBs tracks LEBs that are ineligible for selection for garbage collection, and a second subset of the closed LEBs tracks LEBs that are eligible for selection for garbage collection. The controller continuously migrates closed LEBs from the first subset to the second subset over time. In response to closing a particular LEB, the controller places an identifier of the particular LEB into one of the first and second subsets selected based on a first amount of dummy data programmed into the closed LEBs tracked in the first subset. Thereafter, in response to selection of the particular LEB for garbage collection, the controller performs garbage collection on the particular LEB.
    Type: Application
    Filed: May 2, 2018
    Publication date: November 7, 2019
    Inventors: ROMAN A. PLETKA, NIKOLAOS PAPANDREOU, SASA TOMIC, NIKOLAS IOANNOU
  • Patent number: 10459839
    Abstract: A controller of a non-volatile memory tracks identifiers of logical erase blocks (LEBs) for which programming has closed. A first subset of the closed LEBs tracks LEBs that are ineligible for selection for garbage collection, and a second subset of the closed LEBs tracks LEBs that are eligible for selection for garbage collection. The controller continuously migrates closed LEBs from the first subset to the second subset over time. In response to closing a particular LEB, the controller places an identifier of the particular LEB into one of the first and second subsets selected based on a first amount of dummy data programmed into the closed LEBs tracked in the first subset. Thereafter, in response to selection of the particular LEB for garbage collection, the controller performs garbage collection on the particular LEB.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: October 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Roman A. Pletka, Nikolaos Papandreou, Sasa Tomic, Nikolas Ioannou
  • Patent number: 10453537
    Abstract: A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages including at least a first page and a second page. A controller of the non-volatile memory determines a first calibration interval for a first read voltage threshold defining a bit value in the first page and a different second calibration interval for a second read voltage threshold defining a bit value in the second page. The second calibration interval has a shorter duration than the first calibration interval. The controller calibrates the first and second read voltage thresholds for the plurality of memory cells in the non-volatile memory based on the determined first and second calibration intervals.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Matt Reuter, Sasa Tomic, Nikolaos Papandreou, Timothy Fisher, Aaron D. Fry, Roman A. Pletka, Nikolas Ioannou, Charalampos Pozidis
  • Patent number: 10437670
    Abstract: A computer-implemented method, according to one embodiment, includes: receiving a write command to write data, the write command being received from a log structure array at a host location. The computer-implemented method also includes: extracting metadata information from the received write command; sequentially adding the extracted metadata information to a metadata buffer; extracting parity information from the received write command; adding the extracted parity information to a parity buffer; sending the data corresponding to the received write command to memory; determining whether an open segment in the memory which corresponds to the write command has been filled; updating the parity buffer with the metadata information included in the metadata buffer in response to determining that the open segment has been filled; and destaging the metadata information from the metadata buffer and parity information from the parity buffer to a physical storage location in the memory.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ioannis Koltsidas, Charles J. Camp, Nikolas Ioannou, Roman A. Pletka, Antonios K. Kourtis, Sasa Tomic, Radu I. Stoica, Christopher Dennett, Andrew D. Walls
  • Publication number: 20190278643
    Abstract: Non-volatile memory block management. A method according to one embodiment includes calculating an error count margin threshold for each of the at least some non-volatile memory blocks of a plurality of non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the at least some of the non-volatile memory blocks has been exceeded.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 12, 2019
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Roman Pletka, Sasa Tomic