Patents by Inventor Roman A. Pletka

Roman A. Pletka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180059941
    Abstract: In one embodiment, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the processing circuit to perform a method that includes determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block. The one or more overall threshold voltage shift values are stored. The method also includes reading one or more TVS values from a non-volatile controller memory, and resetting a program/erase cycle count since last calibration after calibrating the one or more overall threshold voltage shift values. The one or more TVS? values and the program/erase cycle count since last calibration are stored to the non-volatile controller memory.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 1, 2018
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic
  • Publication number: 20180059940
    Abstract: A computer program product according to one embodiment includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processing circuit to cause the circuitry to perform a method including determining, after writing data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values. One or more overall threshold voltage shift values for the data written to the non-volatile memory block are calculated, the values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The overall threshold voltage shift values are stored. A base threshold voltage shift (TVSBASE) value, the one or more TVS? values, or both the TVSBASE value and the one or more TVS? values are re-calibrated during a background health check after a predetermined number of background health checks without calibration are performed.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 1, 2018
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis, Sasa Tomic
  • Patent number: 9904607
    Abstract: A controller-implemented method, according to one embodiment, includes: restoring a valid snapshot of a LPT from the non-volatile random access memory, examining each journal entry from at least one journal beginning with a most recent one of the journal entries in a most recent one of the at least one journal and working towards an oldest one of the journal entries in an oldest one of the at least one journal, the journal entries corresponding to updates made to one or more entries of the LPT, determining whether a current LPT entry which corresponds to a currently examined journal entry has already been updated, using the currently examined journal entry to update the current LPT entry in response to determining that the current LPT entry has not already been updated, and discarding the currently examined journal entry in response to determining that the current LPT entry has already been updated.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Roman A. Pletka, Lincoln T. Simmons, Sasa Tomic
  • Patent number: 9898215
    Abstract: In at least one embodiment, a non-volatile memory array including a plurality of blocks each including a plurality of physical pages is controlled by a controller. The controller implements a plurality of nested page retirement classes each defined by a respective one of a plurality of different nested subsets of page indices of physical pages within the plurality of blocks that are to be considered retired from use. For each block among the plurality of blocks, the controller updating an indication of a page retirement class to which the block belongs in response to detection of a retirement-causing error in a data page stored in a physical page of the block. The controller forms block stripes for storing data from the plurality of blocks based on the page retirement classes of the blocks.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Nikolas Ioannou, Thomas Parnell, Roman A. Pletka, Sasa Tomic
  • Publication number: 20180046376
    Abstract: A computer-implemented method, according to one embodiment, includes: assigning data having a first heat to a first data stream, assigning data having a second heat to a second data stream, determining an anticipated throughput of each of the first and second data streams, assigning a first number of logical erase blocks of non-volatile memory to the first data stream based on the anticipated throughput of the first data stream, and assigning a second number of logical erase blocks of non-volatile memory to the second data stream based on the anticipated throughput of the second data stream. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Application
    Filed: October 19, 2017
    Publication date: February 15, 2018
    Inventors: Nikolas Ioannou, Roman A. Pletka, Sasa Tomic
  • Patent number: 9892128
    Abstract: Techniques for selecting a storage node of a storage system to store data include applying a first function to at least some data chunks of an extent to provide respective first values for each of the at least some data chunks. A storage node, included within multiple storage nodes of a storage system, is selected to store the extent based on a majority vote derived from the respective first values.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Nikolas Ioannou, Ioannis Koltsidas, Roman A. Pletka, Cheng-Chung Song, Radu Stoica, Sasa Tomic, Andrew D. Walls
  • Publication number: 20180039536
    Abstract: A computer-implemented method, according to one embodiment, includes: detecting at least one read of a logical page straddled across codewords, storing an indication of a number of detected reads of the straddled logical page, and relocating the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page. When relocated, the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Application
    Filed: October 19, 2017
    Publication date: February 8, 2018
    Inventors: Charles J. Camp, Timothy J. Fisher, Nikolas Ioannou, Thomas Parnell, Roman A. Pletka, Sasa Tomic
  • Patent number: 9886208
    Abstract: A computer-implemented method is provided which includes: assigning data having a first heat to a first data stream, assigning data having a second heat to a second data stream, determining an anticipated throughput of each of the first and second data streams, assigning a first number of logical erase blocks of non-volatile memory to the first data stream based on the anticipated throughput of the first data stream, and assigning a second number of logical erase blocks of non-volatile memory to the second data stream based on the anticipated throughput of the second data stream. The number of logical erase blocks assigned to the data streams may be statically assigned, or may be adjusted dynamically based on at least one of temporal stream throughput, stream stall events, a current workload, or other factors. The non-volatile memory may include NAND flash memory, and wear leveling may be performed on all open logical erase blocks prior to assigning the first and second numbers of erase blocks.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Nikolas Ioannou, Roman A. Pletka, Sasa Tomic
  • Patent number: 9870285
    Abstract: An apparatus, according to one embodiment, includes: one or more memory devices, each memory device comprising non-volatile memory configured to store data, and a memory controller connected to the one or more memory devices. The memory controller is configured to: detect at least one read of a logical page straddled across codewords, store an indication of a number of detected reads of the straddled logical page, and relocate the straddled logical page to a different physical location in response to the number of detected reads of the straddled logical page, wherein the logical page is written to the different physical location in a non-straddled manner. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: January 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Nikolas Ioannou, Thomas Parnell, Roman A. Pletka, Sasa Tomic
  • Patent number: 9864523
    Abstract: In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS?) values configured to track temporary changes with respect to changes in the underlying threshold voltage distributions due to retention and/or read disturb errors. One or more overall threshold voltage shift values is calculated for the data written to the non-volatile memory block, the one or more overall threshold voltage shift values being a function of the one or more TVS? values to be used when writing data to the non-volatile memory block. The one or more overall threshold voltage shift values are stored.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Nikolaos Papandreou, Thomas Parnell, Roman Pletka, Charalampos Pozidis, Sasa Tomic
  • Patent number: 9858141
    Abstract: Techniques for data deduplication in a data storage system include comparing a first attribute of a received data page to first attributes of one or more stored data pages. In response to the first attribute matching one of the first attributes, a second attribute of the received data page is compared to second attributes of the one or more data pages. In response to the second attribute of the received data page matching one of the second attributes, a fingerprint of the received data page is compared to fingerprints of the one or more data pages. In response to the fingerprint of the received data page matching one of the fingerprints, the received data page is discarded and replaced with a reference to the corresponding data page already stored in the storage system. In response to first attribute, the second attribute, or the fingerprint of the received data page not matching, the received data page is stored.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Fisher, Nikolas Ioannou, Thomas Parnell, Roman A. Pletka, Sasa Tomic
  • Patent number: 9857986
    Abstract: In at least one embodiment, a controller of a non-volatile memory array including a plurality of subdivisions stores write data within the non-volatile memory array utilizing a plurality of block stripes of differing numbers of blocks, where all of the blocks within each block stripe are drawn from different ones of the plurality of subdivisions. The controller builds new block stripes for storing write data from blocks selected based on estimated remaining endurances of blocks in each of the plurality of subdivisions.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Jason Ma, Roman A. Pletka, Lincoln T. Simmons, Sasa Tomic
  • Publication number: 20170364448
    Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation.
    Type: Application
    Filed: August 31, 2017
    Publication date: December 21, 2017
    Inventors: Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao Y. Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
  • Publication number: 20170351614
    Abstract: A system, according to one embodiment, includes: non-volatile memory; a non-volatile memory controller having a cache; and logic integrated with and/or executable by the non-volatile memory controller, the logic being configured to: retrieve a physical block address corresponding to a logic block address; extract information from the physical block address; perform a lookup operation in cache using the extracted information; perform a range check of the physical block address in response to the lookup operation succeeding; and read data from the cache in response to the range check succeeding. An architecture of the cache supports separation of data streams, in addition to supporting parallel writes to different non-volatile memory channels. The cache architecture also supports pipelining of the parallel writes to different non-volatile memory planes. The non-volatile memory controller is also configured to perform a direct memory lookup in the cache based on a physical block address.
    Type: Application
    Filed: August 22, 2017
    Publication date: December 7, 2017
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman Pletka, Sasa Tomic, Andrew D. Walls
  • Publication number: 20170351698
    Abstract: Techniques for selecting a storage node of a storage system to store data include applying a first function to at least some data chunks of an extent to provide respective first values for each of the at least some data chunks. A storage node, included within multiple storage nodes of a storage system, is selected to store the extent based on a majority vote derived from the respective first values.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 7, 2017
    Inventors: NIKOLAS IOANNOU, IOANNIS KOLTSIDAS, ROMAN A. PLETKA, CHENG-CHUNG SONG, RADU STOICA, SASA TOMIC, ANDREW D. WALLS
  • Patent number: 9830277
    Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao Y. Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
  • Publication number: 20170315865
    Abstract: Techniques for data deduplication in a data storage system include comparing a first attribute of a received data page to first attributes of one or more stored data pages. In response to the first attribute matching one of the first attributes, a second attribute of the received data page is compared to second attributes of the one or more data pages. In response to the second attribute of the received data page matching one of the second attributes, a fingerprint of the received data page is compared to fingerprints of the one or more data pages. In response to the fingerprint of the received data page matching one of the fingerprints, the received data page is discarded and replaced with a reference to the corresponding data page already stored in the storage system. In response to first attribute, the second attribute, or the fingerprint of the received data page not matching, the received data page is stored.
    Type: Application
    Filed: February 21, 2017
    Publication date: November 2, 2017
    Inventors: TIMOTHY J. FISHER, NIKOLAS IOANNOU, THOMAS PARNELL, ROMAN A. PLETKA, SASA TOMIC
  • Patent number: 9785561
    Abstract: An I/O enclosure module is provided with one or more I/O enclosures having a plurality of slots for receiving electronic devices. A host adapter is connected a first slot of the I/O enclosure module and is configured to connect a host to the I/O enclosure. A device adapter is connected to a second slot of the I/O enclosure module and is configured to connect a storage device to the I/O enclosure module. A flash cache is connected to a third slot of the I/O enclosure module and includes a flash-based memory configured to cache data associated with data requests handled through the I/O enclosure module. A primary processor complex manages data requests handled through the I/O enclosure module by communicating with the host adapter, device adapter, and flash cache to manage to the data requests.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kevin J. Ash, Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Yu-Cheng Hsu, Xiaoyu Hu, Joseph S. Hyde, II, Roman A. Pletka, Alfred E. Sanchez
  • Patent number: 9779021
    Abstract: A system according to one embodiment includes non-volatile memory, and a non-volatile memory controller having a cache. An architecture of the cache supports separation of data streams, and the cache architecture supports parallel writes to different non-volatile memory channels. Additionally, the cache architecture supports pipelining of the parallel writes to different non-volatile memory planes. Furthermore, the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address. Other systems, methods, and computer program products are described in additional embodiments.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: October 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Timothy J. Fisher, Aaron D. Fry, Nikolas Ioannou, Ioannis Koltsidas, Roman Pletka, Sasa Tomic, Andrew D. Walls
  • Publication number: 20170279460
    Abstract: In a data storage system, a prior set S of prefix codes for pseudo-dynamic compression as well as data compressed utilizing prior set S are stored. While data compressed utilizing prior set S are stored in the data storage system, the number of prefix codes utilized by the data storage system for pseudo-dynamic compression are augmented. Augmenting the number of codes includes determining a new set S? of prefix codes for pseudo-dynamic compression from a training data set selected from a workload of the data storage system and storing the new set S? in the data storage system with the prior set S.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 28, 2017
    Inventors: CHARLES J. CAMP, CHARALAMPOS POZIDIS, NIKOLAOS PAPANDREOU, ROMAN A. PLETKA, THOMAS MITTELHOLZER, THOMAS PARNELL, TOBIAS BLAETTLER