Abstract: A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die.

Abstract: A semiconductor package including a top-surface metal layer for implementing circuit features provides improvements in top-surface interconnect density, more flexible routing and mounting of top surface semiconductor packages, dies and passive components or a conformal shield cap implementation. The metal layer interconnected with an internal substrate of the semiconductor package by blind vias laser-ablated through the encapsulation and filled with metal. The vias extend from the top surface to an internal package substrate or through the encapsulation to form bottom-side terminals. The metal layer may be formed by circuit patterns and/or terminals embedded within the encapsulation conformal to the top surface by laser-ablating channels in the top surface of the encapsulation and filling the channels with metal. A conformal coating may be applied to the top surface of the semiconductor package over the metal layer to prevent solder bridging to circuit patterns of the metal layer.

Abstract: A method of forming a wafer level package includes attaching a laser-activated dielectric material to an integrated circuit substrate to form an assembly, the integrated circuit substrate including a plurality of electronic components having terminals on first surfaces thereof. The laser-activated dielectric material is laser activated and ablated with a laser to form laser-ablated artifacts in the laser-activated dielectric material and simultaneously to form an electrically conductive laser-activated layer lining the laser-ablated artifacts. The laser-ablated artifacts are filled using an electroless plating process in which an electrically conductive filler material is selectively plated on the laser-activated layer to form an embedded circuit pattern within the laser-activated dielectric material.

Abstract: A method and structure for creating embedded metal features includes embedded trace substrates wherein bias and signal traces are embedded in a first surface of the embedded trace substrate and extend into the body of the embedded trace substrate. The bias trace and signal trace trenches are formed into the substrate body using LASER ablation, or other ablation, techniques. Using ablation techniques to form the bias and signal trace trenches allows for extremely accurate control of the depth, width, shape, and horizontal displacement of the bias and signal trace trenches. As a result, the distance between the bias traces and the signal traces eventually formed in the trenches, and therefore the electrical properties, such as impedance and noise shielding, provided by the bias traces, can be very accurately controlled.

Abstract: A method of forming an embedded electronic component package includes coupling a substrate to a first dielectric layer, strip, or panel, and forming first electrically conductive vias and traces in the first dielectric layer. A cavity is then formed in the first dielectric layer and an electronic component is attached in the cavity. A second dielectric layer, strip, or panel, is then applied to the first dielectric layer, thereby encasing the electronic component in dielectric. Second via apertures are then formed through the second dielectric layer to expose selected electronic component bond pads and/or selected first electrically conductive vias and traces. The second via apertures are then filled with an electrically conductive material to form second electrically conductive vias electrically coupled to selected bond pads and selected first electrically conductive vias and traces.

Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

Abstract: An integrated circuit substrate having embedded lands with etching and plating control features provides improved manufacture of a high-density and low cost mounting and interconnect structure for integrated circuits. The integrated circuit substrate is formed by generating channels in a dielectric material, adding conductive material to fill the channels and then planarizing the conductive material, so that conductors are formed beneath the surface of the dielectric material. Lands are formed with feature shapes that reduce a dimpling effect at etching and/or an over-deposit of material during plating, both due to increased current density at the relatively larger land areas. Feature shapes may be a grid formed with line sizes similar to those employed to form conductive interconnects, so that all features on the substrate have essentially the same line width.

Abstract: A method of forming an electronic component package includes: forming electrically conductive traces for connecting first selected bond pads of a plurality of bond pads on a first surface of an electronic component to corresponding bonding locations formed on a second surface of the electronic component; coupling the first surface of the electronic component to a first surface of a lower dielectric strip; coupling the second surface of the electronic component to a first surface of an upper dielectric strip; forming lower via apertures through the lower dielectric strip to expose second selected bond pads of the plurality of bond pads on the first surface of the electronic component; forming upper via apertures through the upper dielectric strip to expose the bonding locations on the second surface of the electronic component; filling the lower and upper via apertures with an electrically conductive material to form lower and upper vias electrically coupled to the first and second selected bond pads of the pl

Abstract: A method for making an integrated circuit substrate having embedded back-side access conductors and vias provides a high-density mounting and interconnect structure for integrated circuits that is compatible with etched, plated or printed pre-manufactured substrate components. A circuit board or film having a pre-plated, etched or printed circuit, for example a rigid substrate having a Ball Grid Array (BGA) ball-attach pattern, is laser perforated to produce blind vias and/or conductive patterns that provide contact through to conductors of the prefabricated circuit board or film. Existing circuit board and substrate technology is thereby made compatible with laser-embedding technologies, providing the low-cost advantages of existing etching, plating and printing technologies along with a high conductor density associated with laser-embedded circuit technologies.

Abstract: A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of the circuit pattern. Successive resist pattern applications and etching are used to form a via tier atop a circuit pattern that is connected by a thin plane of metal. After the tier is deposited, the thin metal plane is etched to isolate the circuit pattern elements. Dielectric is then deposited and the top half of the via is deposited over the tier. The tier may have a larger or smaller diameter with respect to the other half of the via, so that the via halves may be properly registered. Tin plating may also be used to control the etching process to provide etching control.

Abstract: A method of forming a stackable embedded leadframe package includes coupling an electronic component having bond pads to a substrate; coupling on the substrate a leadframe having a plurality of leads, each lead having a lower mounting portion; encapsulating the electronic component and partially encapsulating the leadframe; singulating each lead; forming via apertures through the substrate to expose the bond pads and the lower mounting portions; and filling the via apertures with an electrically conductive material to form vias electrically coupled to the bond pads and to the lower mounting portions. This permits stacking of electronic components in a small geometry.

Abstract: A method for making an integrated circuit substrate having embedded passive components provides a reduced cost and compact package for a die and one or more passive components. An insulating layer of the substrate is embossed or laser-ablated to generate apertures for insertion of a paste forming the body of the passive component. A resistive paste is used to form resistors and a dielectric paste is used for forming capacitors. A capacitor plate may be deposited at a bottom of the aperture by using a doped substrate material and activating only the bottom wall of the aperture, enabling plating of the bottom wall without depositing conductive material on the side walls of the aperture. Vias may be formed to the bottom plate by using a disjoint structure and conductive paste technology. Connection to the passive components may be made by conductive paste-filled channels forming conductive patterns on the substrate.

Abstract: A method for making an integrated circuit substrate having laser-embedded conductive patterns provides a high-density mounting and interconnect structure for integrated circuits. A dielectric material is injection-molded or laminated over a metal layer that is punched or etched. The metal layer can provide one or more power planes within the substrate. A laser is used to ablate channels on the surfaces of the outer dielectric layer for the conductive patterns. The conductive patterns are electroplated or paste screen-printed and an etchant-resistive material is applied. Finally, a plating material can be added to exposed surfaces of the conductive patterns. An integrated circuit die and external terminals can then be attached to the substrate, providing an integrated circuit having a high-density interconnect.

Abstract: A circuit-on-foil process for manufacturing a laminated semiconductor package substrate having embedded conductive patterns provides a high-density mounting and interconnect structure for semiconductor packages that is manufacturable in volume. A dielectric film is laminated on one or both sides with a foil layer with a circuit pattern disposed on a surface of the foil. The circuit-on-foil layer can be made by laser-ablating a plating resist material and then plating metal atop a foil, or by laser-exposing a photo-sensitive plating resist material and then plating the circuit pattern atop the foil. After lamination, the metal foil is removed by etching or machining to leave only the dielectric and embedded conductors. Vias can be formed between layers of embedded conductors by laser-drilling holes either though the entire substrate or from one side through to at least the bottom of one of the embedded circuit layers, and then filling the hole with metal.

Abstract: A method of forming an electronic component package includes: forming electrically conductive traces for connecting first selected bond pads of a plurality of bond pads on a first surface of an electronic component to corresponding bonding locations formed on a second surface of the electronic component; coupling the first surface of the electronic component to a first surface of a lower dielectric strip; coupling the second surface of the electronic component to a first surface of an upper dielectric strip; forming lower via apertures through the lower dielectric strip to expose second selected bond pads of the plurality of bond pads on the first surface of the electronic component; forming upper via apertures through the upper dielectric strip to expose the bonding locations on the second surface of the electronic component; filling the lower and upper via apertures with an electrically conductive material to form lower and upper vias electrically coupled to the first and second selected bond pads of the pl

Abstract: A method of forming an electronic component package includes coupling a first surface of an electronic component to a first surface of a first dielectric strip, the electronic component comprising bond pads on the first surface; forming first via apertures through the first dielectric strip to expose the bond pads; and filling the first via apertures with an electrically conductive material to form first vias electrically coupled to the bond pads. The bond pads are directly connected to the corresponding first vias without the use of a solder and without the need to form a solder wetting layer on the bond pads.

Abstract: A semiconductor package comprising a substrate having opposed top and bottom surfaces and a conductive pattern formed thereon. Disposed on the top surface of the substrate is a semiconductor die which is electrically connected to the conductive pattern. Also disposed on the top surface of the substrate is a leadframe which is electrically connected to the conductive pattern as well. A package body encapsulates the semiconductor die and partially encapsulates the leadframe such that a portion of the leadframe is exposed in one exterior surface of the package body, thus allowing a second semiconductor package to be stacked upon and electrically connected to the semiconductor package.

Abstract: A semiconductor package including top-surface terminals for mounting another semiconductor package provides a three-dimensional circuit configuration that can provide removable connection of existing grid-array packages having a standard design. A semiconductor die is mounted on an electrically connected to a circuit substrate having terminals disposed on a bottom side for connection to an external system. The die and substrate are encapsulated and vias are laser-ablated or otherwise formed through the encapsulation to terminals on the top surface of the substrate that provide a grid array mounting lands to which another grid array semiconductor package may be mounted. The bottom side of the vias may terminate and electrically connect to terminals on the substrate, terminals on the bottom of the semiconductor package (through terminals) or terminals on the top of the semiconductor die.

Abstract: A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of the circuit pattern. Successive resist pattern applications and etching are used to form a via tier atop a circuit pattern that is connected by a thin plane of metal. After the tier is deposited, the thin metal plane is etched to isolate the circuit pattern elements. Dielectric is then deposited and the top half of the via is deposited over the tier. The tier may have a larger or smaller diameter with respect to the other half of the via, so that the via halves may be properly registered. Tin plating may also be used to control the etching process to provide etching control.

Abstract: An integrated circuit substrate having laser-exposed terminals provides a high-density and low cost mounting and interconnect structure for integrated circuits. The laser-exposed terminals can further provide a selective plating feature by using a dielectric layer of the substrate to prevent plating terminal conductors and subsequently exposing the terminals via laser ablation. A metal layer may be coated on one or both sides with a dielectric material, conductive material embedded within the dielectric to form conductive interconnects and then coating over the conductive material with a conformal protective coating. The protectant is then laser-ablated to expose the terminals. A dielectric film having a metal layer laminated on one side may be etched and plated. Terminals are then laser-exposed from the back side of the metal layer exposing unplated terminals.