Patents by Inventor Rong Lin

Rong Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090211979
    Abstract: Ion chromatography apparatus including (a) a chromatographic column, (b) a source of an aqueous eluent liquid stream, (c) a detector, (d) a recycle line between the detector and the chromatographic column, and (e) a purifying device disposed along the recycle line including ion exchange removal medium. Also, such apparatus with an electrolytic purifying device disposed along the recycle line. Also, methods of using such apparatus.
    Type: Application
    Filed: February 25, 2008
    Publication date: August 27, 2009
    Applicant: DIONEX CORPORATION
    Inventors: Kannan Srinivasan, Rong Lin, Sheetal Bhardwaj, Christopher A. Pohl
  • Patent number: 7572676
    Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: August 11, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Fang-Jun Leu, Shou-Lung Chen, Ching-Wen Hsiao, Shan-Pu Yu, Jyh-Rong Lin, I-Hsuan Peng, Jian-Shu Wu, Hui-Mei Wu, Chien-Wei Chieh
  • Publication number: 20090190992
    Abstract: An ink cartridge structure includes a resilient device coupled to an ink cartridge for absorbing impact energy acting on the ink cartridge for protection of the ink cartridge. The resilient device includes a connection bar mounted to the ink cartridge and is coupled to a retention bar that is accessible by a user with a resilient element therebetween so that the resilient element provides cushioning to the ink cartridge. The connection bar is partially fit into a hollow portion of the retention bar and forms a vent hole that is in communication with the ink cartridge so that when the retention bar, under the resilient support by the resilient element, is manually moved reciprocally with respect to the connection bar, air is pumped, through the vent hole, into the ink cartridge to force the ink contained in the ink cartridge to ward a writing tip.
    Type: Application
    Filed: January 29, 2008
    Publication date: July 30, 2009
    Inventor: RONG-LIN SHEU
  • Publication number: 20090115051
    Abstract: An electronic circuit package has a thin-film circuit integrated with the ceramic substrate. The thin-film circuit includes at least two passive circuit elements joined by an integrated electrical interconnect. At least one active power electronic component mounted on the ceramic substrate and is electrically connected with the integrated thin-film circuit.
    Type: Application
    Filed: November 1, 2007
    Publication date: May 7, 2009
    Inventors: Lap-Wai Lydia Leung, Yu-Chih Chen, Chi Kuen Leung, Jyh-Rong Lin, Chang Hwa Chung
  • Patent number: 7528009
    Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: May 5, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
  • Patent number: 7462560
    Abstract: A process of physical vapor depositing mirror layer with improved reflectivity is disclosed. A wafer is loaded into a PVD tool comprising a degas chamber, a Ti/TiN sputter deposition chamber, a cooling chamber, and an aluminum sputter deposition chamber. A wafer degas process is first performed within the degas chamber. The wafer is then transferred to the Ti/TiN sputter deposition chamber and deposition sputtering a layer of titanium onto the wafer. The wafer is transferred to the cooling chamber and gas cooling the wafer temperature down to 40-50° C. The wafer is then transferred to the aluminum sputter deposition chamber and deposition sputtering a layer of aluminum onto the wafer at 40-50° C. with a backside gas turned off. The deposited layer of aluminum over the wafer has a reflectivity of about 0.925 at wavelength of around 380 nm.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: December 9, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Nien-Chung Chiang, Chih-Sheng Chang, Chun-Hsing Tung, Yi-Tyng Wu, Huai-Hsuan Tsai, Chi-Rong Lin
  • Patent number: 7448815
    Abstract: The mechanical pencil contains a tubular body having a bottom cap and a top cap. Inside the mechanical pencil, a tip element is positioned inside and protrudes from the bottom cap, a clamping mechanism is above the tip element with a spring therebetween, and a sliding mechanism is above the clamping mechanism. A single lead is stored in the sliding mechanism and is held by the clamping mechanism. When the lead outside the tip element is used up and the tip element is pressed, the spring is compressed and a segment of the lead is advanced into the tip element. When the tip element is released, the tip element is pushed downward by the spring and the segment of the lead is brought along with the tip element. By repeating the process a number of times, the lead would be extended out of the tip element.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: November 11, 2008
    Inventor: Rong-Lin Sheu
  • Publication number: 20080245668
    Abstract: Pretreatment method and apparatus to remove matrix ions from a liquid sample, prior to separation of the sample analytes (e.g. by chromatography), by flowing the liquid sample into a sample compartment and stopping the flow. The sample compartment has a wall comprising an ion exchange membrane having exchangeable ions of the same charge as the matrix ions to be removed. A regenerant liquid stream flows through a regenerant flow compartment on the other side of the membrane from said parked liquid sample. Matrix ions in the parked liquid sample are transported across the membrane into the regenerant flow compartment. Suppression may be performed electrolytically and/or chemically. A concentrator column may also be used.
    Type: Application
    Filed: June 17, 2008
    Publication date: October 9, 2008
    Applicant: Dionex Corporation
    Inventors: Kannan Srinivasan, Rong Lin
  • Publication number: 20080226378
    Abstract: A combination pen includes a tubular barrel having two open ends for selectively receiving different stationery devices so that different stationery devices can be combined together with the barrel. The stationery devices received in the barrel can be replaced if desire so that any combination that is desired by a user or that is of practical use can be made with respect to different kinds of stationery devices. The stationary devices can be selectively combined together for saving of space and ease of stowage.
    Type: Application
    Filed: March 15, 2007
    Publication date: September 18, 2008
    Inventor: Rong-Lin Sheu
  • Patent number: 7411306
    Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: August 12, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Fang-Jun Leu, Shou-Lung Chen, Ching-Wen Hsiao, Shan-Pu Yu, Jyh-Rong Lin, I-Hsuan Peng, Jian-Shu Wu, Hui-Mei Wu, Chien-Wei Chieh
  • Patent number: 7399415
    Abstract: Pretreatment method and apparatus to remove matrix ions from a liquid sample, prior to separation of the sample analytes (e.g. by chromatography), by flowing the liquid sample into a sample compartment and stopping the flow. The sample compartment has a wall comprising an ion exchange membrane having exchangeable ions of the same charge as the matrix ions to be removed. A regenerant liquid stream flows through a regenerant flow compartment on the other side of the membrane from said parked liquid sample. Matrix ions in the parked liquid sample are transported across the membrane into the regenerant flow compartment. Suppression may be performed electrolytically and/or chemically. A concentrator column may also be used.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: July 15, 2008
    Assignee: Dionex Corporation
    Inventors: Kannan Srinivasan, Rong Lin
  • Publication number: 20080165186
    Abstract: Systems and methods for visualizing multiple volumes of three-dimensional data. A graphics card is used for voxel intermixing, pixel intermixing and image intermixing, which produces a final-combined image of the three-dimensional data in real time.
    Type: Application
    Filed: January 4, 2008
    Publication date: July 10, 2008
    Applicant: Landmark Graphics Corporation, a Halliburton Company
    Inventor: Jim Ching-Rong Lin
  • Patent number: 7376099
    Abstract: A method for dynamic channel allocation for access points in wireless networks. Communication information of wireless devices is gathered. A network topology formed by the wireless devices is derived according to the communication information. Switch channel indexes for each wireless device are calculated according to the communication information and network topology. Desired wireless devices for switching channels are determined according to the switch channel indexes.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: May 20, 2008
    Assignee: Institute for Information Industry
    Inventors: Yu-Chee Tseng, Chih-Yu Lin, Bing-Rong Lin
  • Patent number: 7356431
    Abstract: A computer-based method for testing an input/output functional board is provided. The method includes the steps of: obtaining control information of the computer; testing devices coupled with the input/output functional board by using the control information; and determining whether the devices work normally according to test results. A related system is also disclosed.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: April 8, 2008
    Assignees: Hong Fu Jin Precision Industry (Shen Zhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Wen-Chih Hsu, Wei Shao, Shao-Rong Lin, Gao-Hui Dai
  • Publication number: 20080029870
    Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
    Type: Application
    Filed: October 5, 2007
    Publication date: February 7, 2008
    Applicant: Industrial Technology Research Institute
    Inventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
  • Patent number: 7294920
    Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: November 13, 2007
    Assignee: Industrial Technology Research Institute
    Inventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
  • Publication number: 20070197018
    Abstract: This invention relates to a wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
    Type: Application
    Filed: April 19, 2007
    Publication date: August 23, 2007
    Applicant: Industrial Technology Research Institute
    Inventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Chih-Ming Tzeng, Jyh-Rong Lin, Shan-Pu Yu
  • Publication number: 20070195188
    Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.
    Type: Application
    Filed: April 25, 2007
    Publication date: August 23, 2007
    Applicant: Industrial Technology Research Institute
    Inventors: Fang-Jun Leu, Shou-Lung Chen, Ching-Wen Hsiao, Shan-Pu Yu, Jyh-Rong Lin, I-Hsuan Peng, Jian-Shu Wu, Hui-Mei Wu, Chien-Wei Chieh
  • Patent number: D558391
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: December 25, 2007
    Inventor: Rong Lin
  • Patent number: D571503
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: June 17, 2008
    Inventor: Rong Lin