Abstract: The present disclosure relates to an embedded flash memory cell having a common source oxide layer with a substantially flat top surface, disposed between a common source region and a common erase gate, and a method of formation. In some embodiments, the embedded flash memory cell has a semiconductor substrate with a common source region separated from a first drain region by a first channel region and separated from a second drain region by a second channel region. A high-quality common source oxide layer is formed by an in-situ steam generation (ISSG) process at a location overlying the common source region. First and second floating gate are disposed over the first and second channel regions on opposing sides of a common erase gate having a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode layer over a lower metal interconnect layer. A dielectric data storage layer having a variable resistance is formed onto the bottom electrode layer in-situ with forming at least a part of the bottom electrode layer. A top electrode layer is formed over the dielectric data storage layer. By forming the dielectric data storage layer in-situ with forming at least a part of the bottom electrode layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

Abstract: A method includes placing a first wafer onto a surface of a first wafer chuck, the first wafer chuck including multiple first profile control zones separated by one or more shared flexible membranes. The method also includes setting a first profile of the surface of the first wafer chuck. Setting a first profile of the surface of the first wafer chuck includes adjusting a first volume of a first profile control zone of the multiple first profile control zones. Setting a first profile of the surface of the first wafer chuck also includes adjusting a second volume of a second profile control zone of the multiple first profile control zones, the first volume of the first profile control zone being adjusted independently from the second volume of the second profile control zone, and the second adjustable volume encircling the first adjustable volume.

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.

Abstract: A method includes forming a selection gate and a control gate for a flash memory cell in a memory device region. The selection gate and the control gate are over a semiconductor substrate. A protection layer is formed to cover the selection gate and the control gate. Stacked layers are formed in a logic device region, wherein the stacked layers extend to overlap the selection gate and the control gate. The stacked layers are patterned to form a gate stack for a logic device in the logic device region. After the patterning, an etching step is performed to etch a residue of the stacked layers in a boundary region of the memory device region. After the etching step, the protection layer is removed from the memory device region. Source and drain regions are formed for each of the flash memory cell and the logic device.

Abstract: The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.

Abstract: A method of manufacturing a capacitive device. The method includes doping a substrate to form a well region, forming M shoulder portions and (M?1) trenches in the substrate, depositing (M?1) sets of stacked layers along an upper surface of each shoulder portion of the M shoulder portions, sidewalls of the (M?1) trenches, and a bottom surface of each trench of the (M?1) trenches, and etching a plurality of contact holes variously exposing the well region or conductive layers of the (M?1) sets of stacked layers by N patterned masks. An m-th trench of the (M?1) trenches is between an m-th shoulder portion and an (m+1)-th shoulder portion of the M shoulder portions. M is a positive integer equal to or greater than 2 and m is a positive integer from 1 to (M?1). N is a positive integer less than M. Each contact hole of the plurality of contact holes is directly on or above a corresponding shoulder portion of the M shoulder portions.

Abstract: A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first surface of a first bonding chuck, loading a second wafer on a second bonding chuck, and bonding the first wafer to the second wafer. The first surface is defined at least in part by a first portion of a first spherical surface and a second portion of a second spherical surface. The first spherical surface has a first radius, and the second spherical surface has a second radius. The first radius is less than the second radius.

Abstract: A system for and a method of bonding a first wafer to a second wafer are provided. A second wafer chuck has a second surface, a profile of the second surface being adjustable by a profile control layer. The first wafer is placed on a first surface of a first wafer chuck, and the second wafer is placed on the second surface of the second wafer chuck. The first wafer and the second wafer are warped prior to bonding to form a first warped wafer and a second warped wafer, respectively. The first warped wafer is bonded to the second warped wafer.

Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell having a reduced leakage current, and an associated apparatus. In some embodiments, the method is performed by forming a bottom electrode over a lower metal interconnect layer using an atomic layer deposition (ALD) process to form at least a top portion of the bottom electrode. A dielectric data storage layer is formed onto the top portion of the bottom electrode in-situ with forming the top portion of the bottom electrode. A top electrode is formed over the dielectric data storage layer, and an upper metal interconnect layer is formed over the top electrode. By forming the top portion of the bottom electrode using an ALD process that is in-situ with the formation of the overlying dielectric data storage layer, leakage current, leakage current distribution and device yield of the RRAM cell are improved.

Abstract: A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first surface of a first bonding chuck, loading a second wafer on a second bonding chuck, and bonding the first wafer to the second wafer. The first surface is defined at least in part by a first portion of a first spherical surface and a second portion of a second spherical surface. The first spherical surface has a first radius, and the second spherical surface has a second radius. The first radius is less than the second radius.

Abstract: A method of forming an IC (integrated circuit) device is provided. The method includes receiving a first wafer including a first substrate and including a plasma-reflecting layer disposed on an upper surface thereof. The plasma-reflecting layer is configured to reflect a plasma therefrom. A dielectric protection layer is formed on a lower surface of a second wafer, wherein the second wafer includes a second substrate. The second wafer is bonded to the first wafer, such that a cavity is formed between the plasma-reflecting layer and the dielectric protection layer. An etch process is performed with the plasma to form an opening extending from an upper surface of the second wafer and through the dielectric protection layer into the cavity. A resulting structure of the above method is also provided.

Abstract: A method for performing a high aspect ratio etch is provided. A semiconductor substrate is provided with a hard mask layer arranged over the semiconductor substrate. A first etch is performed into the hard mask layer to form a hard mask opening exposing the semiconductor substrate. The hard mask opening has a bottom width. A second etch is performed into the semiconductor substrate, through the hard mask opening, to form a substrate opening with a top width that is about equal to the bottom width of the hard mask opening. A protective layer is formed lining a sidewall of the substrate opening. A third etch is performed into the semiconductor substrate, through the hard mask opening, to increase a height of the substrate opening. The top width of the substrate opening remains substantially unchanged during the third etch. A semiconductor structure with a high aspect ratio opening is also provided.

Abstract: A method of manufacturing a capacitive device. The method includes doping a substrate to form a well region, forming M shoulder portions and (M?1) trenches in the substrate, depositing (M?1) sets of stacked layers along an upper surface of each shoulder portion of the M shoulder portions, sidewalls of the (M?1) trenches, and a bottom surface of each trench of the (M?1) trenches, and etching a plurality of contact holes variously exposing the well region or conductive layers of the (M?1) sets of stacked layers by N patterned masks. An m-th trench of the (M?1) trenches is between an m-th shoulder portion and an (m+1)-th shoulder portion of the M shoulder portions. M is a positive integer equal to or greater than 2 and m is a positive integer from 1 to (M?1). N is a positive integer less than M. Each contact hole of the plurality of contact holes is directly on or above a corresponding shoulder portion of the M shoulder portions.

Abstract: A semiconductor device includes an indium gallium nitride layer over an active layer. The semiconductor device further includes an annealed region beneath the indium gallium nitride layer, the annealed region comprising indium atoms driven from the indium gallium nitride layer into the active layer.

Abstract: In a method of forming a split gate memory cell, a sacrificial spacer is formed over a semiconductor substrate. A first layer of conductive material is formed over a top surface and sidewalls of the sacrificial spacer. A first etch back process is formed on the first layer of conductive material to expose the top surface of the sacrificial spacer and upper sidewall regions of the sacrificial spacer. A conformal silicide-blocking layer is then formed which extends over the etched back first layer of conductive material and over the top surface of the sacrificial spacer.

Abstract: The present disclosure relates to a method of forming an RRAM cell having a dielectric data layer that provides good performance, device yield, and data retention, and an associated apparatus. In some embodiments, the method is performed by forming an RRAM film stack having a bottom electrode layer disposed over a semiconductor substrate, a top electrode layer, and a dielectric data storage layer disposed between the bottom electrode and the top electrode. The dielectric data storage layer has a performance enhancing layer with a hydrogen-doped oxide and a data retention layer having an aluminum oxide. The RRAM film stack is then patterned according to one or more masking layers to form a top electrode and a bottom electrode, and an upper metal interconnect layer is formed at a position electrically contacting the top electrode.

Abstract: A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first surface of a first bonding chuck, loading a second wafer on a second bonding chuck, and bonding the first wafer to the second wafer. The first surface is defined at least in part by a first portion of a first spherical surface and a second portion of a second spherical surface. The first spherical surface has a first radius, and the second spherical surface has a second radius. The first radius is less than the second radius.

Abstract: A semiconductor device includes a substrate, a first layer over the substrate, a second layer over the first layer, and a third layer over the second layer. The third layer has a first portion and a second portion. The first portion of the third layer is separated from the second portion of the third layer. The semiconductor device also includes a first blended region beneath the first portion of the third layer. The first blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device further includes a second blended region beneath the second portion of the third layer. The second blended region includes aluminum atoms drawn from the first layer into at least the second layer. The semiconductor device also includes a source contact and a drain contact.