Abstract: A semiconductor device includes an indium gallium nitride layer over an active layer. The semiconductor device further includes an annealed region beneath the indium gallium nitride layer, the annealed region comprising indium atoms driven from the indium gallium nitride layer into the active layer.

Abstract: A method includes placing a first wafer onto a surface of a first wafer chuck, the first wafer chuck including multiple first profile control zones separated by one or more shared flexible membranes. The method also includes setting a first profile of the surface of the first wafer chuck. Setting a first profile of the surface of the first wafer chuck includes adjusting a first volume of a first profile control zone of the multiple first profile control zones. Setting a first profile of the surface of the first wafer chuck also includes adjusting a second volume of a second profile control zone of the multiple first profile control zones, the first volume of the first profile control zone being adjusted independently from the second volume of the second profile control zone, and the second adjustable volume encircling the first adjustable volume.

Abstract: A device includes a metal layer comprising a plurality of bottom electrode features. The device further includes a Magnetic Tunnel Junction (MTJ) stack layer comprising a plurality of MTJ stack features, each of the MTJ stack features disposed on a top surface of one of the plurality of bottom electrode features. The device further includes sidewall structures that extend along side surfaces of both the bottom electrode features and the MTJ stack features.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a bottom electrode via (BEVA), a recap layer on the BEVA, and a magnetic tunneling junction (MTJ) layer over the recap layer. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA. The recap layer overlaps a top surface of the lining layer and a top surface of the electroplated copper.

Abstract: The present disclosure relates to a method for debonding a pair of bonded substrates. In the method, a debonding apparatus is provided comprising a wafer chuck, a flex wafer assembly, and a set of separating blades. The pair of bonded substrates is placed upon the wafer chuck so that a first substrate of the bonded substrate pair is in contact with a chuck top surface. The flex wafer assembly is placed above the bonded substrate pair so that its first surface is in contact with an upper surface of a second substrate of the bonded substrate pair. A pair of separating blades having different thicknesses is inserted between the first and second substrates from edges of the pair of bonded substrates diametrically opposite to each other while the second substrate is concurrently pulled upward until the flex wafer assembly flexes the second substrate from the first substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.

Abstract: A method for performing a high aspect ratio etch is provided. A semiconductor substrate is provided with a hard mask layer arranged over the semiconductor substrate. A first etch is performed into the hard mask layer to form a hard mask opening exposing the semiconductor substrate. The hard mask opening has a bottom width. A second etch is performed into the semiconductor substrate, through the hard mask opening, to form a substrate opening with a top width that is about equal to the bottom width of the hard mask opening. A protective layer is formed lining a sidewall of the substrate opening. A third etch is performed into the semiconductor substrate, through the hard mask opening, to increase a height of the substrate opening. The top width of the substrate opening remains substantially unchanged during the third etch. A semiconductor structure with a high aspect ratio opening is also provided.

Abstract: A method includes patterning a metal layer to form a plurality of bottom electrode features, forming a Magnetic Tunnel Junction (MTJ) stack by a line-of-sight deposition process such that a first portion of the MTJ stack is formed on the bottom electrode features, and a second portion of the MTJ stack is formed on a level that is different than a top surface of the bottom electrode features, and performing a removal process to remove the second portion of the MTJ stack while leaving the first portion of the MTJ stack substantially intact.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a bottom electrode via (BEVA), a recap layer on the BEVA, and a magnetic tunneling junction (MTJ) layer over the recap layer. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA. The recap layer overlaps a top surface of the lining layer and a top surface of the electroplated copper.

Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.

Abstract: An integrated circuit (IC) device is provided. The IC device includes a first die including a first substrate and a second die including a second substrate. A plasma-reflecting layer is included on an upper surface of the first die. The plasma-reflecting layer is configured to reflect a plasma therefrom. The second substrate is bonded to the first die so as to form a cavity, wherein a lower surface of the cavity is lined by the plasma-reflecting layer. A dielectric protection layer is present on a lower surface of the second die and lines the upper surface of the cavity. A material of the second substrate has a first etch rate for the plasma and a material of the dielectric protection layer has a second etch rate for the plasma. The second etch rate is less than the first etch rate.

Abstract: Some embodiments of the present disclosure relate to method of forming a memory device. In some embodiments, the method may be performed by forming a floating gate over a first dielectric on a substrate. A control gate is formed over the floating gate and first and second spacers are formed along sidewalls of the control gate. The first and second spacers extend past outer edges of an upper surface of the floating gate. An etching process is performed on the first and second spacers to remove a portion of the first and second spacers that extends past the outer edges of the upper surface of the floating gate along an interface between the first and second spacers and the floating gate.

Abstract: The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a bottom electrode via (BEVA), a recap layer on the BEVA, and a magnetic tunneling junction (MTJ) layer over the recap layer. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA. The recap layer overlaps a top surface of the lining layer and a top surface of the electroplated copper.

Abstract: A semiconductor arrangement and methods of formation are provided. The semiconductor arrangement includes a micro-electro mechanical system (MEMS). A via opening is formed through a substrate, first dielectric layer and a first plug of the MEMS. The first plug comprises a first material, where the first material has an etch selectivity different than an etch selectivity of the first dielectric layer. The different etch selectivity of first plug allows the via opening to be formed relatively quickly and with a relatively high aspect ratio and desired a profile, as compared to forming the via opening without using the first plug.

Abstract: An exemplary method includes forming a common source region in a substrate, and forming an isolation feature over the common source region. The common source region is disposed between the substrate and the isolation feature. The common source region and the isolation feature span a plurality of active regions of the substrate. A gate, such as an erase gate, may be formed after forming the common source region. In some implementations, the common source region is formed by etching the substrate to form a saw-tooth shaped recess region (or a U-shaped recess region) and performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region (or the U-shaped recess region), such that the common source region has a sawtooth profile (or a U-shaped profile).

Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

Abstract: A bonding chuck is discussed with methods of using the bonding chuck and tools including the bonding chuck. A method includes loading a first wafer on first surface of a first bonding chuck, loading a second wafer on a second bonding chuck, and bonding the first wafer to the second wafer. The first surface is defined at least in part by a first portion of a first spherical surface and a second portion of a second spherical surface. The first spherical surface has a first radius, and the second spherical surface has a second radius. The first radius is less than the second radius.

Abstract: Some embodiments of the present disclosure relate to a memory device, which includes a floating gate formed over a channel region of a substrate, and a control gate formed over the floating gate. First and second spacers are formed along sidewalls of the control gate, and extend over outer edges of the floating gate to form a non-uniform overhang, which can induce a wide distribution of erase speeds of the memory device. To improve the erase speed distribution, an etching process is performed on the first and second spacers prior to erase gate formation. The etching process removes the overhang of the first and second spacers at an interface between a bottom region of the first and second spacers and a top region of the floating gate to form a planar surface at the interface, and improves the erase speed distribution of the memory device.

Abstract: A method of forming an IC (integrated circuit) device is provided. The method includes receiving a first wafer including a first substrate and including a plasma-reflecting layer disposed on an upper surface thereof. The plasma-reflecting layer is configured to reflect a plasma therefrom. A dielectric protection layer is formed on a lower surface of a second wafer, wherein the second wafer includes a second substrate. The second wafer is bonded to the first wafer, such that a cavity is formed between the plasma-reflecting layer and the dielectric protection layer. An etch process is performed with the plasma to form an opening extending from an upper surface of the second wafer and through the dielectric protection layer into the cavity. A resulting structure of the above method is also provided.

Abstract: A method of forming a semiconductor structure of a control gate is provided, including depositing a first dielectric layer overlying a substrate, forming a surface modification layer from the first dielectric layer; and forming semiconductor dots on the surface modification layer. The surface modification layer has a bonding energy to the semiconductor dots less than the bonding energy between the first dielectric layer and the semiconductor dots. Therefore the semiconductor dots have higher density to form on the surface modification layer than that to directly form on the first dielectric layer. And a semiconductor device is also provided to tighten threshold voltage (Vt) and increase programming efficiency.

Abstract: Semiconductor structures are presented. An exemplary semiconductor structure comprises a common source region having a sawtooth profile, and a flat erase gate disposed above the common source region. Methods of making semiconductor structures are also presented. An exemplary method comprises forming a plurality of trenches in a substrate thereby forming a plurality of active regions; forming a common source region in the substrate in a direction perpendicular to the active regions. The exemplary method further comprises, after forming the common source region, forming a dielectric feature on the substrate thereby filling the trenches and forming a plurality of shallow trench isolation features, and forming an erase gate on the dielectric feature.