Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.

Abstract: A flow sensing module is provided for determining a flow rate of a fluid flowing through a flow channel. The flow sensing module may include an integrated flow restrictor, sometimes including a plurality of concentric ribs defining a plurality of orifices shaped to match the curvature of the wall of the flow channel. A first sensing port may open into the flow channel upstream of the flow restrictor, and a second sensing port may open into the flow channel downstream of the flow restrictor. A flow rate of a fluid flowing through the flow channel may be determining using a differential pressure between the first and second ports created by the flow restrictor, either using a flow sensor or a pressure sensor. The particular arrangement and relative dimensions of the orifices of the flow restrictor and the pressure ports can result in substantially reduced noise.

Abstract: An interference-shielding Hall plate (100) includes a shielding plate (10) and a Hall plate body (20). A first Hall sensor (210) is provided on a first surface (201) of the Hall plate body to detect magnet position of a motor, and a second Hall sensor (220) is provided on a second surface (202) of the Hall plate body to detect magnet position of an external device that cooperates with the motor. The shielding plate is welded to the Hall plate body to avoid influence of the magnet of a motor body on the second Hall sensor and interference of the magnet of an external device, which cooperates with the motor, on the first Hall sensor. Without affecting detection of the position of the motor body magnet, the motor can operate normally.

Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise an identical first fin structure, the PG2A and the PG2B comprise an identical second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2.

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Abstract: A continuously variable transmission (CVT) includes a power transmission mechanism and at least one conical disk. The power transmission mechanism has a contact surface, and the power transmission mechanism includes a plurality of engaging elements. The plurality of engaging elements are retractably disposed on the contact surface. The disk surface of the conical disk has a plurality of engaging walls capable of engaging with the engaging elements. The continuously variable transmission is able to transmit power by way of engagement, such that the coupling between the power transmission mechanism and the conical disk is more stable. Thus, the continuously variable transmission is adaptable to high torsion application.

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Abstract: A high-density semiconductor structure includes a substrate, a bit line and a first memory unit. The bit line, disposed on the substrate, has a first side and a second side. The first memory unit includes a first transistor, a first capacitor, a second transistor and a second capacitor. The first transistor disposed on the substrate has a first terminal and a second terminal. The first terminal connects the bit line. The first capacitor connects the second terminal of the first transistor. The second transistor disposed on the substrate has a third terminal and a fourth terminal. The third terminal connects the bit line. The second capacitor connects the fourth terminal of the second transistor. The first capacitor and the second capacitor are separated from the bit line in a direction perpendicular to an extending direction of the bit line and located on the first side of the bit line.

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Abstract: A speech-synthesizing device includes a hierarchical prosodic module, a prosody-analyzing device, and a prosody-synthesizing unit. The hierarchical prosodic module generates at least a first hierarchical prosodic model. The prosody-analyzing device receives a low-level linguistic feature, a high-level linguistic feature and a first prosodic feature, and generates at least a prosodic tag based on the low-level linguistic feature, the high-level linguistic feature, the first prosodic feature and the first hierarchical prosodic model. The prosody-synthesizing unit synthesizes a second prosodic feature based on the hierarchical prosodic module, the low-level linguistic feature and the prosodic tag.

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Abstract: A semiconductor layout structure includes at least a first signal line and a pair of Vss lines. The first signal line and the pair of Vss lines are extended along a first direction, and the Vss lines are arranged along a second direction. The first direction and the second direction are perpendicular to each other. The Vss lines are arranged at respective two sides of the first signal line.

Abstract: A flow sensing module is provided for determining a flow rate of a fluid flowing through a flow channel. The flow sensing module may include an integrated flow restrictor, sometimes including a plurality of concentric ribs defining a plurality of orifices shaped to match the curvature of the wall of the flow channel. A first sensing port may open into the flow channel upstream of the flow restrictor, and a second sensing port may open into the flow channel downstream of the flow restrictor. A flow rate of a fluid flowing through the flow channel may be determining using a differential pressure between the first and second ports created by the flow restrictor, either using a flow sensor or a pressure sensor. The particular arrangement and relative dimensions of the orifices of the flow restrictor and the pressure ports can result in substantially reduced noise.

Abstract: A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.