Abstract: A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices.

Abstract: The invention provides a mask pattern. The mask pattern comprises at least a continuous pattern. Each of the continuous patterns has a first pattern, a second pattern and a set of assistance patterns. The assistant patterns are located between the first pattern to the second pattern. The first pattern, the assistant patterns and the second pattern together form a closed opening.

Abstract: A method of problem case packaging handling consists collecting manufacturing problem information from entities associated with fabrication of a semiconductor product; and distributing the manufacturing problem information into problem cases which are stored in a problem database, each problem case representing a respective manufacturing problem and being associated with manufacturing problem information related to that problem case.

Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

Abstract: The invention provides a mask pattern. The mask pattern comprises at least a continuous pattern. Each of the continuous patterns has a first pattern, a second pattern and a set of assistance patterns. The assistant patterns are located between the first pattern to the second pattern. The first pattern, the assistant patterns and the second pattern together form a closed opening.

Abstract: A method of monitoring physiological status is periodically inspecting physiological status of a user, obtaining a physiological signal value, and determining whether the physiological signal value is normal or not. The method includes collecting a plurality of specific physiological values, calculating a reference value and a reference range according to the specific physiological values, and determining and displaying whether the physiological signal value of the specific section of the next inspection period falls within the reference value and the reference range according to the reference value and the reference range. The update of the above reference value and reference range is determined when a next physiological value is collected, so as to maintain the accuracy of the reference value and reference range. A care device of monitoring physiological status is also included in the embodiment.

Abstract: In embodiments of the present invention improved capabilities are described for a method of cleaning a solid fuel that may provide a starting solid fuel sample data relating to one or more characteristics of a solid fuel to be treated by a solid fuel treatment facility; may provide a desired solid fuel characteristic; may compare the starting solid fuel sample data relating to one or more characteristics to the desired solid fuel characteristic to determine a solid fuel composition delta; may determine an operational treatment parameter for the operation of the solid fuel treatment facility to clean the solid fuel based at least in part on the solid fuel composition delta; and may monitor contaminants emitted from the solid fuel during treatment of the solid fuel and regulating the operational treatment parameter with respect thereto to create a cleaned solid fuel.

Abstract: A circuit board and a fabrication method thereof. Providing the insulating layer with a first conductive layer formed thereon; wherein the insulating layer was formed on a core substrate with at least one patterned circuit layer thereon. A first resist layer is applied on a first conductive layer, forming first openings to expose the first conductive layer. A first patterned circuit layer, including conductive pads and traces, is formed in the first openings. A second resist layer is applied to cover the traces, and a conductive post is formed on each conductive pad. The first and second resist layers and the first conductive layer underneath the first resist layer are removed. A dielectric material layer is formed on the insulating layer with first patterned circuit layer, forming second openings to expose the conductive posts. A second conductive layer is formed on the dielectric material layer and in the second openings.

Abstract: An embedded semiconductor chip structure and a method for fabricating the same are proposed. The structure comprises: a carrier board, therewith a plurality of through openings formed in the carrier board, and through trenches surrounding the through openings in the same; a plurality of semiconductor chips received in the through openings of the carrier board. Subsequently, cutting is processed via the through trenches. Thus, the space usage of the circuit board and the layout design are more efficient. Moreover, shaping time is also shortened.

Abstract: An interface card includes a bracket, a circuit board including a first side and a second side, at least one connector connected to the bracket and the first side of the circuit board, and a control chip positioned on the second side of the circuit board.

Abstract: A circuit board structure and a method for fabricating the same are proposed. A plurality of conductive bumps and a first solder mask are formed on a carrier board, and the first solder mask is filled in the gaps between the conductive bumps and the conductive bumps are exposed. A first circuit layer and a first heat sink are formed on the first solder mask and the conductive bumps. A second heat sink is formed on the first heat sink, and a dielectric layer is formed on the first circuit layer and the first solder mask except the first and second heat sinks. A second circuit layer is formed on the dielectric layer and is electrically conductive to the first circuit layer. A third heat sink is formed on the second heat sink and a heat sink used for a chip mounting thereon is embedded in the dielectric layer. Therefore, the dimension of the circuit board is reduced and it is conformed to the dimension minimization progress of electronic devices.

Abstract: A structure of a circuit board and a method for fabricating the same are proposed. A first and a second dielectric layers are formed on a first and a second carrier boards respectively, and a first and a second circuit layers are formed on the first and second dielectric layer respectively. Then, between the first circuit layer of the first carrier board and the second circuit layer of the second carrier board is laminated a third dielectric layer, and thus the first circuit layer is embedded between the first and the third dielectric layers, and the second circuit layer is embedded between the second and the third dielectric layers. The two carrier boards are removed to form a core board with the first and the second circuit layers. Afterwards, a third and a fourth circuit layers are formed on the first and the second dielectric layers respectively.

Abstract: A method of fabricating electroplate solder on an organic circuit board for forming flip chip joints and board to board solder joints is disclosed. In the method, there is initially provided an organic circuit board including a surface bearing electrical circuitry that includes at least one contact pad. A solder mask layer that is placed on the board surface and patterned to expose the pad. Subsequently, a metal seed layer is deposited by physical vapor deposition, chemical vapor deposition, electroless plating with the use of catalytic copper, or electroplating with the use of catalytic copper, over the board surface. A resist layer with at least an opening located at the pad is formed over the metal seed layer. A solder material is then formed in the opening by eletroplating. Finally, the resist and the metal seed layer beneath the resist are removed.

Abstract: The specification and drawings present a new method, system, apparatus and software product for signaling parameters of multiple buffers by a terminal to a server and determining multiple buffer status of the terminal by the server using these parameters, e.g., for an adequate rate adaptation of multimedia streaming services provided to the terminal by the server. The terminal can be (but is not limited to) a computer, a communication device, a wireless communication device, a portable electronic device, a mobile electronic device, a mobile phone, etc.

Abstract: Disclosed are compositions and methods relating to a human group 1 CD1 transgenic mouse.

Abstract: A method of problem case packaging handling consists collecting manufacturing problem information from entities associated with fabrication of a semiconductor product; and distributing the manufacturing problem information into problem cases which are stored in a problem database, each problem case representing a respective manufacturing problem and being associated with manufacturing problem information related to that problem case.

Abstract: Measurements are taken of moisture, BTU/lb (British Thermal Units per pound), ash, forms of sulfur, volatile material, grindability, and absorption properties of any of a wide variety of mine-run solid fuels. Using that information, a dry electromagnetic process technology has been developed that can be controlled and monitored to selectively alter and enhance solid fuel properties for the application in question. Specific changes include altering the mechanical structure and chemical composition of solid fuels such as coal, coal coke or petroleum coke, increasing the BTU/lb to optimum levels, decreasing all forms of sulfur, and decreasing ash, while maintaining the BTU/lb of the fuels. A new family of solid fuel designer coals not found in nature can be produced via these methods and apparatus.

Abstract: An optoelectronic device is disclosed. The optoelectronic device comprises a transparent conductive substrate, an optoelectronic element, and a base. The transparent conductive substrate comprises a transparent plate, a transparent electrode film formed on the transparent plate, and an insulating part formed on the transparent plate. The insulating part divides the transparent electrode film into a first transparent electrode film and a second transparent electrode film that non-conduct each other. The optoelectronic element comprising a positive electrode and a negative electrode is disposed on the transparent conductive substrate and electrically connected to the first transparent electrode film and the second transparent electrode film individually. The base is formed with an opening that has a reflective surface on the bottom of the opening, and the optoelectronic element is held in the opening in a manner of suspending from or connecting with the bottom of the opening.

Abstract: A full-color display device is disclosed. The present invention comprises a plurality of pixel units each comprising a base, a plurality of transparent conductive substrates, a plurality of light emitting elements, and a plurality of electrode parts. The base has at least three openings formed thereon, the bottom of each opening is a reflective surface, and each of the transparent conductive substrates individually covers each opening. Each of the light emitting elements is individually disposed on one side of each transparent conductive substrate and held in each opening. Each of the electrode parts is formed on the base and electrically connected to the electrodes of the light emitting elements and the transparent conductive substrates.

Abstract: A circuit board and a fabrication method thereof. Providing the insulating layer with a first conductive layer formed thereon; wherein the insulating layer was formed on a core substrate with at least one patterned circuit layer thereon. A first resist layer is applied on a first conductive layer, forming first openings to expose the first conductive layer. A first patterned circuit layer, including conductive pads and traces, is formed in the first openings. A second resist layer is applied to cover the traces, and a conductive post is formed on each conductive pad. The first and second resist layers and the first conductive layer underneath the first resist layer are removed. A dielectric material layer is formed on the insulating layer with first patterned circuit layer, forming second openings to expose the conductive posts. A second conductive layer is formed on the dielectric material layer and in the second openings.