Abstract: A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.

Abstract: A continuously variable transmission (CVT) includes a power transmission mechanism and at least one conical disk. The power transmission mechanism has a contact surface, and the power transmission mechanism includes a plurality of engaging elements. The plurality of engaging elements are retractably disposed on the contact surface. The disk surface of the conical disk has a plurality of engaging walls capable of engaging with the engaging elements. The continuously variable transmission is able to transmit power by way of engagement, such that the coupling between the power transmission mechanism and the conical disk is more stable. Thus, the continuously variable transmission is adaptable to high torsion application.

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Abstract: A semiconductor layout structure includes at least a first signal line and a pair of Vss lines. The first signal line and the pair of Vss lines are extended along a first direction, and the Vss lines are arranged along a second direction. The first direction and the second direction are perpendicular to each other. The Vss lines are arranged at respective two sides of the first signal line.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells further includes: a gate structure on the substrate, a plurality of fin structures disposed on the substrate, where each fin structure is arranged perpendicular to the arrangement direction of the gate structure, a first interlayer dielectric (ILD) layer around the gate structure, a first contact plug in the first ILD layer, where the first contact plug is strip-shaped and contacts two different fin structures; and a second ILD layer on the first ILD layer.

Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.

Abstract: A Chinese speech recognition system and method is disclosed. Firstly, a speech signal is received and recognized to output a word lattice. Next, the word lattice is received, and word arcs of the word lattice are rescored and reranked with a prosodic break model, a prosodic state model, a syllable prosodic-acoustic model, a syllable-juncture prosodic-acoustic model and a factored language model, so as to output a language tag, a prosodic tag and a phonetic segmentation tag, which correspond to the speech signal. The present invention performs rescoring in a two-stage way to promote the recognition rate of basic speech information and labels the language tag, prosodic tag and phonetic segmentation tag to provide the prosodic structure and language information for the rear-stage voice conversion and voice synthesis.

Abstract: Methods for deriving a diffusion coefficient and a drift velocity characterizing an ensemble of particles. A time series of images is acquired, and each image is Fourier transformed. An autocorrelation function is computed and fit to an exponential decay for each wave vector on a grid. A model of the diffusion-advection equation allows the decay rate ?, expressed as a dispersion map over the wave vector plane, to yield both a diffusion coefficient and a mean drift velocity. As an example, the particles may be fluorescently excited probes where the probes label intracellular elements.

Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.

Abstract: A speech-synthesizing device includes a hierarchical prosodic module, a prosody-analyzing device, and a prosody-synthesizing unit. The hierarchical prosodic module generates at least a first hierarchical prosodic model. The prosody-analyzing device receives a low-level linguistic feature, a high-level linguistic feature and a first prosodic feature, and generates at least a prosodic tag based on the low-level linguistic feature, the high-level linguistic feature, the first prosodic feature and the first hierarchical prosodic model. The prosody-synthesizing unit synthesizes a second prosodic feature based on the hierarchical prosodic module, the low-level linguistic feature and the prosodic tag.

Abstract: A communication device is disclosed including: an analog-to-digital converter (ADC) for converting an analog input signal into a digital input signal; an equalizer module coupled with the ADC for processing the digital input signal to generate an equalized signal; a data slicer coupled with the equalizer module for generating an output signal based on the equalized signal; and a control unit coupled with the equalizer module and the data slicer; wherein the control unit or the equalizer module preserves at least one signal equalizing parameter of the equalizer module before the equalizer module enters power saving mode, and the equalizer module loads the at least one signal equalizing parameter to operate when the communication device receives a predetermined control signal.

Abstract: Automatic trading of virtual characters in online applications comprises publishing virtual characters by a first user in a trading system that involves verification at an application server and locking of the selected virtual characters at the application server. This can ensure that the trading of virtual characters is true, reliable and prompt, and reduces the loss to users arising from the trading of virtual characters.

Abstract: A circuit board structure and a method for fabricating the same are proposed. The structure includes an insulating protective layer having a plurality of openings in which conductive vias are formed, a patterned circuit layer formed on the surface of the insulating protective layer and electrically connected to the conductive vias in the openings of the insulating protective layer, and a dielectric layer formed on the insulating protective layer and on the surface of the patterned circuit layer, wherein a plurality of openings are formed in the dielectric layer to thereby expose parts of the patterned circuit layer. Accordingly, the present invention reduces the thickness of a circuit board, which reduces package size, improves product performance, and conforms to the developmental trend toward smaller electronic devices.

Abstract: The present disclosure relates to methods and devices for reducing moisture, dust, particulate matter, and/or other contaminates entering a sensor. A sensor assembly may include a housing with an inlet flow port and an outlet flow port. The housing may define a fluid channel extending between the inlet flow port and the outlet flow port, with a sensor positioned in the housing and exposed to the fluid channel. The sensor may be configured to sense a measure related to the flow rate of a fluid flowing through the fluid channel. A hydrophobic filter may be situated in the fluid channel, sometimes upstream of the sensor. When so configured, and during operation of the sensor assembly, a fluid may pass through the inlet flow port, through the hydrophobic filter, across the sensor, and through the outlet flow port.

Abstract: A Chinese speech recognition system and method is disclosed. Firstly, a speech signal is received and recognized to output a word lattice. Next, the word lattice is received, and word arcs of the word lattice are rescored and reranked with a prosodic break model, a prosodic state model, a syllable prosodic-acoustic model, a syllable-juncture prosodic-acoustic model and a factored language model, so as to output a language tag, a prosodic tag and a phonetic segmentation tag, which correspond to the speech signal. The present invention performs rescoring in a two-stage way to promote the recognition rate of basic speech information and labels the language tag, prosodic tag and phonetic segmentation tag to provide the prosodic structure and language information for the rear-stage voice conversion and voice synthesis.

Abstract: The present disclosure relates to methods and devices for reducing moisture, dust, particulate matter, and/or other contaminates entering a sensor. A sensor assembly may include a housing with an inlet flow port and an outlet flow port. The housing may define a fluid channel extending between the inlet flow port and the outlet flow port, with a sensor positioned in the housing and exposed to the fluid channel. The sensor may be configured to sense a measure related to the flow rate of a fluid flowing through the fluid channel. A hydrophobic filter may be situated in the fluid channel, sometimes upstream of the sensor. When so configured, and during operation of the sensor assembly, a fluid may pass through the inlet flow port, through the hydrophobic filter, across the sensor, and through the outlet flow port.

Abstract: A communication device is disclosed including: an analog-to-digital converter (ADC) for converting an analog input signal into a digital input signal; an equalizer module coupled with the ADC for processing the digital input signal to generate an equalized signal; a data slicer coupled with the equalizer module for generating an output signal based on the equalized signal; and a control unit coupled with the equalizer module and the data slicer; wherein the control unit or the equalizer module preserves at least one signal equalizing parameter of the equalizer module before the equalizer module enters power saving mode, and the equalizer module loads the at least one signal equalizing parameter to operate when the communication device receives a predetermined control signal.