Abstract: A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin.

Abstract: A certain type of gates, such as NOT gates, in a logic network are moved to the network boundary (i.e., inputs or outputs), at least in part, by selecting nodes in the network as candidate nodes for choosing among to determine output phase assignments. Such a candidate node is selected in response to non-reconvergence of branches fanning out from the node.

Abstract: At least one certain type of logic gates, such as NOT gates, in a network of logic gates are moved to the network inputs and outputs, by converting the logic gates in the network to certain types of gates, such as AND, OR and NOT gates. A region in the network is identified for selecting, within the region, between propagating the one certain type of gates to a) the network inputs, and b) the network outputs. The region is identified in response to "reconvergent fanout nodes". A reconvergent fanout node defines a loop having two branches which diverge at the node and reconverge thereafter.

Abstract: In designing a logic network a plurality of nodes are identified which define incompatible output phase assignments. Certain of the incompatible nodes are selected for assigning the output phases, so that NOT gates in the fan-out cone of such a selected node are moved to the network outputs. In a further aspect, the selecting is in response to the number of logic gates in the fan-in cones of the incompatible nodes.

Abstract: A machine methodology for designing asynchronous circuits utilizes a modular approach for the synthesis of asynchronous circuits from signal transition graphs, partitions the signal transition graph into a number of simpler and more manageable modules. Each modular graph is then individually solved. The results of the small graphs are then integrated together to provide a solution to the asynchronous circuit design problem as defined by a given asynchronous behavioral specification. A satisfiability solver for Boolean output function utilizing a binary decision diagram is incorporated in one embodiment which is comprised of a structural SAT formula preprocessor and a complete, incremental SAT processor which is specifically designed to find an optimal solution. The preprocessor compresses a large size SAT formula representing a circuit into a number of smaller SAT formulas. Each small size SAT formula is then solved by the BDD SAT processor.