Abstract: An information processing system, computer readable storage medium, and method for accelerated radix sort processing of data elements in an array in memory. The information processing system stores an array of data elements in a buffer memory in an application specific integrated circuit radix sort accelerator. The array has a head end and a tail end. The system radix sort processing, with a head processor, data elements starting at the head end of the array and progressively advancing radix sort processing data elements toward the tail end of the array. The system radix sort processing, with a tail processor, data elements starting at the tail end of the array and progressively advancing radix sort processing data elements toward the head end of the array, the tail processor radix sort processing data elements in the array contemporaneously with the head processor radix sort processing data elements in the array.

Abstract: Systems and methods for sorting a data set. Data items each having a first portion and a second portion is stored. The first and second portions are stored separately and each has a separate set of keys. The first portion has a pointer indicating the second portion. At least some of the first set of keys for each data item is stored in a local memory of a first processor. At least one data stripe set is defined with one stripe within each bucket. An in-place partial bucket radix sort is performed on data items within one data stripe set with a first processor using an initial key. Incorrectly sorted data items are grouped into respective incorrect data item groups within each bucket. A radix sort is then performed using the initial radix on the incorrect data item groups. A first level sorted output is produced.

Abstract: An information processing system, computer readable storage medium, and method for accelerated radix sort processing of data elements in an array in memory. The information processing system stores an array of data elements in a buffer memory in an application specific integrated circuit radix sort accelerator. The array has a head end and a tail end. The system radix sort processing, with a head processor, data elements starting at the head end of the array and progressively advancing radix sort processing data elements toward the tail end of the array. The system radix sort processing, with a tail processor, data elements starting at the tail end of the array and progressively advancing radix sort processing data elements toward the head end of the array, the tail processor radix sort processing data elements in the array contemporaneously with the head processor radix sort processing data elements in the array.

Abstract: Systems and methods for sorting a data set. A data storage is divided into a plurality of buckets that is each associated with a respective key value. A plurality of stripes is identified in each bucket. At least one data stripe set is defined that has one stripe within each respective bucket. An in-place partial bucket radix sort is performed on data items contained within one data stripe set with a first processor using an initial radix. Incorrectly sorted data items are then grouped in each bucket into a respective incorrect data item group within each bucket. A radix sort is then performed using the initial radix on the items within the respective incorrect data item group. A first level sorted output is produced.

Abstract: Access is obtained to a truth table having a plurality of rows, each including a plurality of input bits and a plurality of output bits. At least some rows include don't-care inputs. At least some of the rows are clustered into a plurality of multi-row clusters. At least some of the multi-row clusters are assigned to ternary content-addressable memory modules of a prefabricated programmable memory array. Instructions for interconnecting the ternary content-addressable memory modules with a plurality of input pins of the prefabricated programmable memory array and a plurality of output pins of the prefabricated programmable memory array are specified in a data structure, in order to implement the truth table.

Abstract: Methods and systems for memory-based computing include combining multiple operations into a single lookup table and combining multiple memory-based operation requests into a single read request. Operation result values are read from a multi-operation lookup table that includes result values for a first operation above a diagonal of the lookup table and includes result values for a second operation below the diagonal. Numerical inputs are used as column and row addresses in the lookup table and the requested operation determines which input corresponds to the column address and which input corresponds to the row address. Multiple operations are combined into a single request by combining respective members from each operation into respective inputs an reading an operation result value from a lookup table to produce a combined result output. The combined result output is separated into a plurality of individual result outputs corresponding to the plurality of requests.

Abstract: Systems for memory-based computing include combining multiple operations into a single lookup table and combining multiple memory-based operation requests into a single read request. Operation result values are read from a multi-operation lookup table that includes result values for a first operation above a diagonal of the lookup table and includes result values for a second operation below the diagonal. Numerical inputs are used as column and row addresses in the lookup table and the requested operation determines which input corresponds to the column address and which input corresponds to the row address. Multiple operations are combined into a single request by combining respective members from each operation into respective inputs an reading an operation result value from a lookup table to produce a combined result output. The combined result output is separated into a plurality of individual result outputs corresponding to the plurality of requests.

Abstract: Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.

Abstract: Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.

Abstract: A method for automated synthesis of a parallel prefix device includes determining structural constraints for a given parallel prefix device; generating a plurality of candidate prefix graphs for the parallel prefix device by performing a search of possible prefix graphs meeting the constraints; performing physical synthesis of each of the plurality of candidate prefix graphs to generate performance information for each candidate prefix graph; and determining one or more of the plurality of candidate prefix graphs that meet performance criteria for incorporation into the parallel prefix device.

Abstract: A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other. Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages.

Abstract: Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance.

Abstract: The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs.

Abstract: Systems and methods for relative ordering circuit synthesis are provided herein. One aspect provides for generating at least one circuit design via at least one processor accessible by a computing device; wherein generating at least one circuit design comprises: generating at least one relative order structure based on at least one circuit design layout, the at least one relative order structure comprising at least one placement constraint associated with at least one circuit element; placing the at least one circuit element associated with the at least one placement constraint within a circuit design according to the at least one placement constraint; and placing circuit elements not associated with the at least one placement constraint within the circuit design. Other embodiments and aspects are also described herein.

Abstract: A method for automated synthesis of a parallel prefix device includes determining structural constraints for a given parallel prefix device; generating a plurality of candidate prefix graphs for the parallel prefix device by performing a search of possible prefix graphs meeting the constraints; performing physical synthesis of each of the plurality of candidate prefix graphs to generate performance information for each candidate prefix graph; and determining one or more of the plurality of candidate prefix graphs that meet performance criteria for incorporation into the parallel prefix device.

Abstract: In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy.

Abstract: Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance.

Abstract: The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs.

Abstract: In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy.

Abstract: Two circuits, an original and a modified, are being recognized, with the original circuit having a first logic and the modified circuit having a second logic. The second logic contains at least one desired logic change relative to the first logic. An equivalence line is detected in the original circuit such that the first and second logic are equivalent from the circuit inputs to the equivalence line. At least one point of change is located amongst the logic gates that are neighboring the equivalence line. The points of change are accepted as verified if an observability condition is fulfilled. The observability condition is checked within a Boolean Satisfiability (SAT) formulation. Substitute logic for the verified points of change is derived using SAT and Boolean equation solving techniques, in such manner that the first logic becomes equivalent to the second logic.