Patents by Inventor Rui CHENG

Rui CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013038
    Abstract: Methods of forming self-aligned patterns are described. A film material is deposited on a patterned film to fill and cover features formed by the patterned film. The film material is recessed to a level below the top of the patterned film. The recessed film is converted to a metal film by exposure to a metal precursor followed by volumetric expansion of the metal film.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 14, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Pramit Manna, Yihong Chen, Ziqing Duan, Rui Cheng, Shishi Jiang
  • Patent number: 10886140
    Abstract: Methods of etching film stacks to from gaps of uniform width are described. A film stack is etched through a hardmask. A conformal liner is deposited in the gap. The bottom of the liner is removed. The film stack is selectively etched relative to the liner. The liner is removed. The method may be repeated to a predetermined depth.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: January 5, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Shishi Jiang, Pramit Manna, Bo Qi, Abhijit Basu Mallick, Rui Cheng, Tomohiko Kitajima, Harry S. Whitesell, Huiyuan Wang
  • Publication number: 20200411371
    Abstract: Embodiments of the present disclosure relate to processes for filling trenches. The process includes depositing a first amorphous silicon layer on a surface of a layer and a second amorphous silicon layer in a portion of a trench formed in the layer, and portions of side walls of the trench are exposed. The first amorphous silicon layer is removed. The process further includes depositing a third amorphous silicon layer on the surface of the layer and a fourth amorphous silicon layer on the second amorphous silicon layer. The third amorphous silicon layer is removed. The deposition/removal cyclic processes may be repeated until the trench is filled with amorphous silicon layers. The amorphous silicon layers form a seamless amorphous silicon gap fill in the trench since the amorphous silicon layers are formed from bottom up.
    Type: Application
    Filed: March 7, 2019
    Publication date: December 31, 2020
    Inventors: Xin LIU, Fei WANG, Rui CHENG, Abhijit Basu MALLICK, Robert Jan VISSER
  • Publication number: 20200404788
    Abstract: A FPC board and a method for manufacturing the same and an OLED display device are provided. The FPC board includes a substrate, a first wire layer disposed on one side of the substrate, a circuit board terminal disposed at an edge on one side of the substrate and connected to the first wire layer, and a first protective layer covering the first wire layer. The thickness of the circuit board terminal is larger than the sum of the thicknesses of the first wire layer and the first protective layer. When the FPC board is connected to the OLED panel, one side of the base substrate on which the panel terminal is provided is opposite to one side of the substrate on which the circuit board terminal is provided, such that the base substrate overlaps with the substrate to connect the circuit board terminal and the panel terminal.
    Type: Application
    Filed: February 21, 2019
    Publication date: December 24, 2020
    Applicant: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Rui XIONG, Jiangkun CHENG
  • Publication number: 20200373159
    Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.
    Type: Application
    Filed: April 20, 2020
    Publication date: November 26, 2020
    Inventors: Takehito KOSHIZAWA, Rui CHENG, Tejinder SINGH, Hidetaka OSHIO
  • Publication number: 20200335339
    Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.
    Type: Application
    Filed: May 5, 2020
    Publication date: October 22, 2020
    Inventors: Tzu-shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KEDLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE
  • Publication number: 20200335338
    Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.
    Type: Application
    Filed: March 17, 2020
    Publication date: October 22, 2020
    Inventors: Tzu-Shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KADLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE
  • Publication number: 20200335334
    Abstract: Methods for depositing a metal film on a doped amorphous silicon layer as a nucleation layer and/or a glue layer on a substrate. Some embodiments further comprise the incorporation of a glue layer to increase the ability of the doped amorphous silicon layer and metal layer to stick to the substrate.
    Type: Application
    Filed: October 9, 2018
    Publication date: October 22, 2020
    Inventors: Rui Cheng, Yihong Chen, Yong Wu, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 10811303
    Abstract: Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a seam-less film is formed. Some embodiments include optional film doping and film treatment (e.g., ion implantation and annealing).
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 20, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Pramit Manna, Ludovic Godet, Rui Cheng, Erica Chen, Ziqing Duan, Abhijit Basu Mallick, Srinivas Gandikota
  • Publication number: 20200321210
    Abstract: Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.
    Type: Application
    Filed: February 21, 2020
    Publication date: October 8, 2020
    Inventors: Meenakshi GUPTA, Rui CHENG, Srinivas GUGGILLA, Karthik JANAKIRAMAN, Diwakar N. KEDLAYA, Zubin HUANG
  • Patent number: 10784107
    Abstract: Methods of forming self-aligned patterns are described. A film material is deposited on a patterned film to fill and cover features formed by the patterned film. The film material is recessed to a level below the top of the patterned film. The recessed film is converted to a metal film by exposure to a metal precursor followed by volumetric expansion of the metal film.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: September 22, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Pramit Manna, Yihong Chen, Ziqing Duan, Rui Cheng, Shishi Jiang
  • Publication number: 20200266052
    Abstract: Aspects of the disclosure provide a method including depositing an underlayer comprising silicon oxide over a substrate, depositing a polysilicon liner on the underlayer, and depositing an amorphous silicon layer on the polysilicon liner. Aspects of the disclosure provide a device intermediate including a substrate, an underlayer comprising silicon oxide formed over the substrate, a polysilicon liner disposed on the underlayer, and an amorphous silicon layer disposed on the polysilicon liner.
    Type: Application
    Filed: February 19, 2020
    Publication date: August 20, 2020
    Inventors: Krishna NITTALA, Rui CHENG, Karthik JANAKIRAMAN, Praket Prakash JHA, Jinrui GUO, Jingmei LIANG
  • Publication number: 20200258720
    Abstract: Systems and methods of using pulsed RF plasma to form amorphous and microcrystalline films are discussed herein. Methods of forming films can include (a) forming a plasma in a process chamber from a film precursor and (b) pulsing an RF power source to cause a duty cycle on time (TON) of a duty cycle of a pulse generated by the RF power source to be less than about 20% of a total cycle time (TTOT) of the duty cycle to form the film. The methods can further include (c) depositing a first film interlayer on a substrate in the process chamber; (d) subsequent to (c), purging the process chamber; and (e) subsequent to (d), introducing a hydrogen plasma to the process chamber. Further in the method, (b)-(e) are repeated to form a film. The film can have an in-film hydrogen content of less than about 10%.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 13, 2020
    Inventors: Krishna NITTALA, Diwakar N. KEDLAYA, Karthik JANAKIRAMAN, Yi YANG, Rui CHENG
  • Publication number: 20200260611
    Abstract: A water-cooled motor controller includes a capacitor, a water-cooled plate, and a power module stacked in a controller housing. The power module is fixedly connected to the water-cooled plate. The water-cooled plate is provided with a cooling medium flow channel on one side facing the power module, and the other side of the water-cooling plate on which the cooling medium flow channel faces away from the power module side contacts the capacitor through an insulating and thermally conductive material for heat exchange. The water-cooled plate and the controller housing are fixedly connected to each other with a cooling medium passage provided therebetween. A cooling medium flows in from the controller housing, and then flows out of the controller housing after being heat exchanged by the water-cooled plate. The present invention utilizes upper and lower surfaces of the water-cooled plate to dissipate heat from the capacitor and the power module simultaneously.
    Type: Application
    Filed: December 26, 2018
    Publication date: August 13, 2020
    Inventors: Lei LIU, Hongxin WU, Rui SHANG, Yang YANG, Yong CHENG, Jianhua MAO
  • Publication number: 20200258471
    Abstract: A spliced display device and a configuration method thereof, and a display server and a control method thereof are provided. The configuration method may be applied to a spliced display device, and the spliced display device includes a plurality of displays spliced together in an array. The configuration method includes: receiving display control information sent by a display server in a preset protocol format, wherein the display control information at least includes position setting information; and configuring the plurality of displays according to the display control information.
    Type: Application
    Filed: June 19, 2019
    Publication date: August 13, 2020
    Inventors: Jianting WANG, Jinhui CHENG, Wei ZHANG, Zhanchang BU, Junning SU, Jianzi HE, Rui GUO
  • Publication number: 20200248303
    Abstract: Methods for gapfill of high aspect ratio features are described. A first film is deposited on the bottom and upper sidewalls of a feature. The first film is etched from the sidewalls of the feature and the first film in the bottom of the feature is treated to form a second film. The deposition, etch and treat processes are repeated to fill the feature.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Inventors: Rui Cheng, Abhijit Basu Mallick, Pramit Manna
  • Publication number: 20200234932
    Abstract: Embodiments of the present disclosure generally relate to a pedestal for increasing temperature uniformity in a substrate supported thereon. The pedestal comprises a body having a heater embedded therein. The body comprises a patterned surface that includes a first region having a first plurality of posts extending from a base surface of the body at a first height, and a second region surrounding the central region having a second plurality of posts extending from the base surface at a second height that is greater than the first height, wherein an upper surface of each of the first plurality of posts and the second plurality of posts are substantially coplanar and define a substrate receiving surface.
    Type: Application
    Filed: December 4, 2019
    Publication date: July 23, 2020
    Inventors: Venkata Sharat Chandra PARIMI, Zubin HUANG, Jian LI, Satish RADHAKRISHNAN, Rui CHENG, Diwakar N. KEDLAYA, Juan Carlos ROCHA-ALVAREZ, Umesh M. KELKAR, Karthik JANAKIRAMAN, Sarah Michelle BOBEK, Prashant Kumar KULSHRESHTHA, Vinay K. PRABHAKAR, Byung Seok KWON
  • Publication number: 20200230229
    Abstract: Embodiments of immunogens based on the HIV-1 Env fusion peptide and methods of their use and production are disclosed. Nucleic acid molecules encoding the immunogens are also provided. In several embodiments, the immunogens can be used to generate an immune response to HIV-1 Env in a subject, for example, to treat or prevent an HIV-1 infection in the subject.
    Type: Application
    Filed: October 3, 2017
    Publication date: July 23, 2020
    Applicant: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY, DEPARTMENT OF HEALTH AND HUMAN SERVIC
    Inventors: Peter Kwong, Rui Kong, Tongqing Zhou, John Mascola, Kai Xu, Michael Gordon Joyce, Cheng Cheng, Gwo-Yu Chuang, Kevin Liu, Baoshan Zhang, Li Ou, Wing-Pui Kong, Yongping Yang
  • Patent number: 10707286
    Abstract: An OLED device and a method of preparing the same are provided, the OLED device including: a substrate; a first source electrode on the substrate, the first source electrode having a first side surface; a first insulating layer on the first source electrode, the first insulating layer having a second side surface intersecting with an upper surface of the first source electrode and the first side surface of the first source electrode, with at least one of an angle between the first side surface and the upper surface of the substrate and an angle between the second side surface and the upper surface of the substrate being an acute angle; an active layer on the substrate, the active layer covering the first side surface and the second side surface; a gate insulating layer on the active layer; an anode on the gate insulating layer; a light emitting functional layer on the anode; and a cathode on the light emitting functional layer, the cathode including a first drain region covering the first insulating layer and
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: July 7, 2020
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qinghe Wang, Dongfang Wang, Tongshang Su, Rui Peng, Leilei Cheng, Yang Zhang, Jun Wang, Guangyao Li, Liangchen Yan, Guangcai Yuan
  • Publication number: 20200209812
    Abstract: A practical method for short-term operations of large-scale hydropower plants divides all hydropower plants into three categories using operation characteristics such as system hierarchy, space attributes, task requirements, and schedule particularity. A strategy for adjusting spillage based on peak-shaving response and a strategy for equal load reduction in off-peak hours check and adjust power generation of hydropower plants with specified dispatching modes. For medium- and small-sized cascaded hydropower plants, the load distribution among plants is optimized with an objective of minimizing total power release subject to control condition of total generation profile. For large-size cascaded hydropower plants, an optimization model for peak-shaving operations and a method for balancing power plants with equal load rate are combined to respond to system peak demands and guarantee power balance in all periods.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 2, 2020
    Inventors: Jianjian SHEN, Chuntian CHENG, Rui CAO, Qianqian SHEN