Patents by Inventor Rui CHENG

Rui CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250242848
    Abstract: A folding frame comprises a first stand assembly, a second stand assembly and a bottom frame assembly, wherein the first stand assembly comprises two groups of first telescopic assemblies and a group of first connecting assemblies; any one of the two groups of first telescopic assemblies comprises a first connecting rod and a first telescopic rod, and the first connecting rod and the first telescopic rod are distributed in a cross shape; the first connecting assembly consists of two first connecting rockers; the second stand assembly comprises two groups of second telescopic assemblies; any one of the two groups of second telescopic assemblies comprises a second connecting rod and a second telescopic rod, and the second connecting rod and the second telescopic rod are distributed in a cross shape.
    Type: Application
    Filed: January 29, 2024
    Publication date: July 31, 2025
    Inventors: Rui CHENG, Xuefeng ZHENG
  • Publication number: 20250246450
    Abstract: Embodiments of the disclosure provided herein include systems and methods for increasing tensile stress in tungsten layers in a semiconductor device manufacturing scheme. The system includes a processing chamber defining a processing volume, a gas delivery system fluidly coupled to the processing chamber, and a controller having instructions stored thereon for performing a method of processing a plurality of substrates when executed by one or more processors. The method includes cleaning the processing chamber, seasoning the processing chamber with a non-oxygen containing gas, receiving a substrate into the processing volume of the processing chamber fluidly coupled to the gas delivery system, performing a pre-treatment process on the substrate within the processing chamber, and depositing a tungsten-containing layer onto the substrate.
    Type: Application
    Filed: January 28, 2025
    Publication date: July 31, 2025
    Inventors: Aykut AYDIN, Rui CHENG, Xinhai HAN, Karthik JANAKIRAMAN
  • Patent number: 12365986
    Abstract: Method for depositing amorphous silicon materials are provide and include generating a plasma within a plasma unit in fluid communication with a process chamber and flowing the plasma through an ion suppressor to produce an activated fluid containing reactive species and neutral species. The activated fluid either contains no ions or contains a lower concentration of ions than the plasma. The method further includes flowing the activated fluid into a first inlet of a dual channel showerhead within the process chamber and flowing a silicon precursor into a second inlet of the dual channel showerhead. Thereafter, the method includes flowing a mixture of the activated fluid and the silicon precursor out of the dual channel showerhead and forming an amorphous silicon layer on a substrate disposed in the process chamber.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 22, 2025
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zubin Huang, Rui Cheng, Chen-An Chen, Karthik Janakiraman
  • Publication number: 20250230541
    Abstract: Methods for forming a metal carbide liner in features formed in a substrate surface are described. Each of the features extends a distance into the substrate from the substrate surface and have a bottom and at least one sidewall. The methods include depositing a metal carbide liner in the feature of the substrate surface with a plurality of high-frequency ratio-frequency (HFRF) pulses. Semiconductor devices with the metal carbide liner and methods for filling gaps using the metal carbide liner are also described.
    Type: Application
    Filed: February 19, 2025
    Publication date: July 17, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Rui Cheng, Guoqing Li, Qinghua Zhao
  • Publication number: 20250207284
    Abstract: Disclosed herein is a method for fabricating a nanowire array on an uneven or curved surface. A pliable, porous scaffold is used to hold a liquid electrolyte, creating s semi-solid electrolyte that is used to transfer pressure to a template disposed on the target surface to cause the template to conform to and bond with the target surface to substantially eliminate the gap therebetween, such that a robust and controllable growth of the nanowire array can be realized.
    Type: Application
    Filed: May 9, 2023
    Publication date: June 26, 2025
    Applicant: CARNEGIE MELLON UNIVERSITY
    Inventors: SHENG SHEN, RUI CHENG
  • Patent number: 12334358
    Abstract: Exemplary processing methods may include depositing a boron-containing material or a silicon-and-boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The methods may include etching portions of the boron-containing material or the silicon-and-boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The methods may also include removing remaining portions of the boron-containing material or the silicon-and-boron-containing material from the substrate with a fluorine-containing precursor.
    Type: Grant
    Filed: July 18, 2021
    Date of Patent: June 17, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Takehito Koshizawa, Karthik Janakiraman, Rui Cheng, Krishna Nittala, Menghui Li, Ming-Yuan Chuang, Susumu Shinohara, Juan Guo, Xiawan Yang, Russell Chin Yee Teo, Zihui Li, Chia-Ling Kao, Qu Jin, Anchuan Wang
  • Patent number: 12325910
    Abstract: Methods for depositing film comprising cyclical exposure of a substrate surface to a precursor and a degas environment to remove gas evolved from the film. Some embodiments further comprise the incorporation poisoning the top of a feature to inhibit film growth at the top of the feature. Some embodiments further comprising etching a portion of the film deposited at the top of a feature between cycles to increase gap-fill uniformity.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: June 10, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Yihong Chen, Rui Cheng, Pramit Manna, Kelvin Chan, Karthik Janakiraman, Abhijit Basu Mallick, Srinivas Gandikota
  • Publication number: 20250140566
    Abstract: Thicker hardmasks are typically needed for etching deeper capacitor holes in a DRAM structure. Instead of increasing the hardmask thickness, hardmasks may instead be formed with an increased etch selectivity relative to the underlying semiconductor structure. For example, boron-based hardmasks may be formed that include a relatively high percentage of boron (e.g., greater than 90%). The etch selectivity of the hardmask may be improved by performing an ion implant process using different types of ions. The ion implant may take place before or after opening the hardmask with the pattern for the DRAM capacitor holes. Some designs may also tilt the semiconductor substrate relative to the ion implant process and rotate the substrate to provide greater ion penetration throughout a depth of the openings in the hardmask.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 1, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Aykut Aydin, Rajesh Prasad, Fenglin Wang, Rui Cheng, Karthik Janakiraman, Kyu-Ha Shim
  • Publication number: 20250125145
    Abstract: Exemplary methods of forming a silicon-containing material may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber and include one or more features. The methods may include generating plasma effluents of the silicon-containing precursor in the processing region. The methods may include depositing a silicon-containing material on a vertically extending portion and a horizontally extending portion of the feature. Methods include soaking the deposited silicon-containing material with a second silicon-containing material.
    Type: Application
    Filed: October 11, 2023
    Publication date: April 17, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Tianyang Li, Hang Yu, Rui Cheng, Deenesh Padhi, Woongsik Nam
  • Publication number: 20250112046
    Abstract: Exemplary semiconductor processing methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber. The methods may include flowing a boron-containing precursor into the substrate processing region of the semiconductor processing chamber. The methods may include depositing a boron-and-silicon-containing layer on a substrate in the substrate processing region of the semiconductor processing chamber. The boron-and-silicon-containing layer may be characterized by an increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer opposite the first surface. A flow rate of the boron-containing precursor may be increased during the deposition of the boron-and-silicon-containing layer.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Yi Yang, Krishna Nittala, Rui Cheng, Karthik Janakiraman, Diwakar Kedlaya, Zubin Huang, Aykut Aydin
  • Patent number: 12255054
    Abstract: Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: March 18, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Venkata Sharat Chandra Parimi, Zubin Huang, Manjunath Veerappa Chobari Patil, Nitin Pathak, Yi Yang, Badri N. Ramamurthi, Truong Van Nguyen, Rui Cheng, Diwakar Kedlaya
  • Patent number: 12256582
    Abstract: The present disclosure provides a display panel, a manufacturing method thereof and a display device. The display panel includes: a base substrate including a display region, a wiring region surrounding the display region and a bonding region located at a side of the display region; a light-emitting element arranged in the display region and including a cathode; and a first line and at least one second line in the wiring region, the first line being coupled to the cathode of the light-emitting element, two ends of the second line being coupled to the first line in the bonding region, and the first line and the second line being coupled through at least two via holes at an opposite side of the bonding region.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: March 18, 2025
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Rui Cheng, Yunpeng Zhang, Lele Sun
  • Publication number: 20250056763
    Abstract: Systems and methods are provided for monitoring fluid line in a vehicle configured to remove heat from an electronic device with a coolant. The systems may include a pump configured to flow the coolant through the fluid line, a sensing device configured to sense vibrations in the fluid line, and a controller that is configured to: receive vehicle state data, determine a recommended flow rate of the coolant based on the vehicle state data, determine vibration signal thresholds based on the vehicle state data and the recommended flow rate, initiate operation of the pump to flow the coolant at the recommended flow rate, determine whether the flow of the coolant is stable, receive sensor data indicative of the vibrations, determine signal characteristic(s) of the vibrations while the flow is stable, and initiate a remedial action based on a comparison of the signal characteristic(s) to the vibration signal thresholds.
    Type: Application
    Filed: August 10, 2023
    Publication date: February 13, 2025
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Pulasti Bandara, Karl Bo Albert Mikkelsen, Rui Cheng
  • Publication number: 20250037996
    Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more recessed features along the substrate and a seam or void may be defined by the silicon-containing material within at least one of the one or more recessed features along the substrate. The methods may also include treating the silicon-containing material with a hydrogen-containing gas, such as plasma effluents of the hydrogen-containing gas, which may cause a size of the seam or void to be reduced.
    Type: Application
    Filed: October 11, 2024
    Publication date: January 30, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Qinghua Zhao, Rui Cheng, Ruiyun Huang, Dong Hyung Lee, Aykut Aydin, Karthik Janakiraman
  • Patent number: 12205818
    Abstract: Embodiments of the present technology include semiconductor processing methods to make boron-and-silicon-containing layers that have a changing atomic ratio of boron-to-silicon. The methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber, and also flowing a boron-containing precursor and molecular hydrogen (H2) into the substrate processing region of the semiconductor processing chamber. The boron-containing precursor and the H2 may be flowed at a boron-to-hydrogen flow rate ratio. The flow rate of the boron-containing precursor and the H2 may be increased while the boron-to-hydrogen flow rate ratio remains constant during the flow rate increase. The boron-and-silicon-containing layer may be deposited on a substrate, and may be characterized by a continuously increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer furthest from the substrate.
    Type: Grant
    Filed: March 15, 2024
    Date of Patent: January 21, 2025
    Assignee: Applied Materials, Inc.
    Inventors: Yi Yang, Krishna Nittala, Rui Cheng, Karthik Janakiraman, Diwakar Kedlaya, Zubin Huang, Aykut Aydin
  • Publication number: 20250022425
    Abstract: The present disclosure provides a display apparatus, a display panel and a preparation method. The display panel includes a base substrate, a driving circuit provided on a side of the base substrate and a multi-layer metal layer: the base substrate includes a display region and a peripheral region located on a periphery of the display region; the driving circuit includes a peripheral circuit and a pixel circuit, the peripheral circuit is located at the peripheral region, the pixel circuit is located at the display region, and the peripheral circuit is connected with the pixel circuit and configured to provide a driving signal to the pixel circuit; the peripheral circuit includes a plurality of signal lines distributed in at least two metal layers.
    Type: Application
    Filed: March 8, 2022
    Publication date: January 16, 2025
    Applicants: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Erlong SONG, Hailong YAN, Jingli ZHANG, Yagui GAO, Kai ZHANG, Rui CHENG, Kunyan SHI, Yafei CHEN
  • Patent number: 12197479
    Abstract: Disclosed are a semantic matching and retrieval method and apparatus. The semantic matching and retrieval method includes steps of obtaining both the vector representation of a query text and the vector representation of a document text; obtaining the final vector representation of the query text; obtaining the final vector representation of the document text; calculating, based on the final vector representation of the query text and the final vector representation of the document text, the similarity score between the query text and the document text; and selecting, based on the similarity scores between the query text and a plurality of document texts, a document text matching the query text from the plurality of document texts.
    Type: Grant
    Filed: December 20, 2023
    Date of Patent: January 14, 2025
    Assignee: Ricoh Company, Ltd.
    Inventors: Rui Cheng, Bin Dong, Shanshan Jiang, Lu Luo, Lei Ding
  • Patent number: 12183578
    Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: December 31, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Takehito Koshizawa, Rui Cheng, Tejinder Singh, Hidetaka Oshio
  • Patent number: D1073240
    Type: Grant
    Filed: January 27, 2025
    Date of Patent: April 29, 2025
    Inventor: Rui Cheng
  • Patent number: D1073241
    Type: Grant
    Filed: January 27, 2025
    Date of Patent: April 29, 2025
    Inventor: Rui Cheng