Patents by Inventor Rui CHENG

Rui CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411371
    Abstract: Embodiments of the present disclosure relate to processes for filling trenches. The process includes depositing a first amorphous silicon layer on a surface of a layer and a second amorphous silicon layer in a portion of a trench formed in the layer, and portions of side walls of the trench are exposed. The first amorphous silicon layer is removed. The process further includes depositing a third amorphous silicon layer on the surface of the layer and a fourth amorphous silicon layer on the second amorphous silicon layer. The third amorphous silicon layer is removed. The deposition/removal cyclic processes may be repeated until the trench is filled with amorphous silicon layers. The amorphous silicon layers form a seamless amorphous silicon gap fill in the trench since the amorphous silicon layers are formed from bottom up.
    Type: Application
    Filed: March 7, 2019
    Publication date: December 31, 2020
    Inventors: Xin LIU, Fei WANG, Rui CHENG, Abhijit Basu MALLICK, Robert Jan VISSER
  • Publication number: 20200373159
    Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.
    Type: Application
    Filed: April 20, 2020
    Publication date: November 26, 2020
    Inventors: Takehito KOSHIZAWA, Rui CHENG, Tejinder SINGH, Hidetaka OSHIO
  • Publication number: 20200335334
    Abstract: Methods for depositing a metal film on a doped amorphous silicon layer as a nucleation layer and/or a glue layer on a substrate. Some embodiments further comprise the incorporation of a glue layer to increase the ability of the doped amorphous silicon layer and metal layer to stick to the substrate.
    Type: Application
    Filed: October 9, 2018
    Publication date: October 22, 2020
    Inventors: Rui Cheng, Yihong Chen, Yong Wu, Abhijit Basu Mallick, Srinivas Gandikota
  • Publication number: 20200335339
    Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.
    Type: Application
    Filed: May 5, 2020
    Publication date: October 22, 2020
    Inventors: Tzu-shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KEDLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE
  • Publication number: 20200335338
    Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.
    Type: Application
    Filed: March 17, 2020
    Publication date: October 22, 2020
    Inventors: Tzu-Shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KADLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE
  • Patent number: 10811303
    Abstract: Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a seam-less film is formed. Some embodiments include optional film doping and film treatment (e.g., ion implantation and annealing).
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: October 20, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Pramit Manna, Ludovic Godet, Rui Cheng, Erica Chen, Ziqing Duan, Abhijit Basu Mallick, Srinivas Gandikota
  • Publication number: 20200321210
    Abstract: Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.
    Type: Application
    Filed: February 21, 2020
    Publication date: October 8, 2020
    Inventors: Meenakshi GUPTA, Rui CHENG, Srinivas GUGGILLA, Karthik JANAKIRAMAN, Diwakar N. KEDLAYA, Zubin HUANG
  • Patent number: 10784107
    Abstract: Methods of forming self-aligned patterns are described. A film material is deposited on a patterned film to fill and cover features formed by the patterned film. The film material is recessed to a level below the top of the patterned film. The recessed film is converted to a metal film by exposure to a metal precursor followed by volumetric expansion of the metal film.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: September 22, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Pramit Manna, Yihong Chen, Ziqing Duan, Rui Cheng, Shishi Jiang
  • Publication number: 20200266052
    Abstract: Aspects of the disclosure provide a method including depositing an underlayer comprising silicon oxide over a substrate, depositing a polysilicon liner on the underlayer, and depositing an amorphous silicon layer on the polysilicon liner. Aspects of the disclosure provide a device intermediate including a substrate, an underlayer comprising silicon oxide formed over the substrate, a polysilicon liner disposed on the underlayer, and an amorphous silicon layer disposed on the polysilicon liner.
    Type: Application
    Filed: February 19, 2020
    Publication date: August 20, 2020
    Inventors: Krishna NITTALA, Rui CHENG, Karthik JANAKIRAMAN, Praket Prakash JHA, Jinrui GUO, Jingmei LIANG
  • Publication number: 20200258720
    Abstract: Systems and methods of using pulsed RF plasma to form amorphous and microcrystalline films are discussed herein. Methods of forming films can include (a) forming a plasma in a process chamber from a film precursor and (b) pulsing an RF power source to cause a duty cycle on time (TON) of a duty cycle of a pulse generated by the RF power source to be less than about 20% of a total cycle time (TTOT) of the duty cycle to form the film. The methods can further include (c) depositing a first film interlayer on a substrate in the process chamber; (d) subsequent to (c), purging the process chamber; and (e) subsequent to (d), introducing a hydrogen plasma to the process chamber. Further in the method, (b)-(e) are repeated to form a film. The film can have an in-film hydrogen content of less than about 10%.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 13, 2020
    Inventors: Krishna NITTALA, Diwakar N. KEDLAYA, Karthik JANAKIRAMAN, Yi YANG, Rui CHENG
  • Publication number: 20200248303
    Abstract: Methods for gapfill of high aspect ratio features are described. A first film is deposited on the bottom and upper sidewalls of a feature. The first film is etched from the sidewalls of the feature and the first film in the bottom of the feature is treated to form a second film. The deposition, etch and treat processes are repeated to fill the feature.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Inventors: Rui Cheng, Abhijit Basu Mallick, Pramit Manna
  • Publication number: 20200234932
    Abstract: Embodiments of the present disclosure generally relate to a pedestal for increasing temperature uniformity in a substrate supported thereon. The pedestal comprises a body having a heater embedded therein. The body comprises a patterned surface that includes a first region having a first plurality of posts extending from a base surface of the body at a first height, and a second region surrounding the central region having a second plurality of posts extending from the base surface at a second height that is greater than the first height, wherein an upper surface of each of the first plurality of posts and the second plurality of posts are substantially coplanar and define a substrate receiving surface.
    Type: Application
    Filed: December 4, 2019
    Publication date: July 23, 2020
    Inventors: Venkata Sharat Chandra PARIMI, Zubin HUANG, Jian LI, Satish RADHAKRISHNAN, Rui CHENG, Diwakar N. KEDLAYA, Juan Carlos ROCHA-ALVAREZ, Umesh M. KELKAR, Karthik JANAKIRAMAN, Sarah Michelle BOBEK, Prashant Kumar KULSHRESHTHA, Vinay K. PRABHAKAR, Byung Seok KWON
  • Publication number: 20200211834
    Abstract: Methods for forming the silicon boron nitride layer are provided. The method includes positioning a substrate on a pedestal in a process region within a process chamber, heating a pedestal retaining the substrate, and introducing a first flow of a first process gas and a second flow of a second process gas to the process region. The first flow of the first process gas contains silane, ammonia, helium, nitrogen, argon, and hydrogen. The second flow of the second process gas contains diborane and hydrogen. The method also includes forming a plasma concurrently with the first flow of the first process gas and the second flow of the second process gas to the process region and exposing the substrate to the first process gas, the second process gas, and the plasma to deposit the silicon boron nitride layer on the substrate.
    Type: Application
    Filed: December 23, 2019
    Publication date: July 2, 2020
    Inventors: Chuanxi YANG, Hang YU, Sanjay KAMATH, Deenesh PADHI, Honggun KIM, Euhngi LEE, Zubin HUANG, Diwakar N. KEDLAYA, Rui CHENG, Karthik JANAKIRAMAN
  • Patent number: 10699903
    Abstract: Methods for gapfilling semiconductor device features, such as high aspect ratio trenches, with amorphous silicon film are provided. First, a substrate having features formed in a first surface thereof is positioned in a processing chamber. A conformal deposition process is then performed to deposit a conformal silicon liner layer on the sidewalls of the features and the exposed first surface of the substrate between the features. A flowable deposition process is then performed to deposit a flowable silicon layer over the conformal silicon liner layer. A curing process is then performed to increase silicon density of the flowable silicon layer. Methods described herein generally improve overall etch selectivity by the conformal silicon deposition and the flowable silicon deposition two-step process to realize seam-free gapfilling between features with high quality amorphous silicon film.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 30, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Pramit Manna, Shishi Jiang, Rui Cheng, Abhijit Basu Mallick
  • Publication number: 20200194571
    Abstract: Embodiments described herein generally relate to doping of three dimensional (3D) structures on a substrate. In some embodiments, a conformal dopant containing film may be deposited over the 3D structures. Suitable dopants that may be incorporated in the film include halogen atoms. The film may be subsequently annealed to diffuse the dopants into the 3D structures.
    Type: Application
    Filed: August 28, 2018
    Publication date: June 18, 2020
    Inventors: Rui Cheng, Yi Yang, Karthik Janakiraman, Abhijit Basu Mallick
  • Publication number: 20200161171
    Abstract: Generally, examples described herein relate to methods and processing systems for forming isolation structures (e.g., shallow trench isolations (STIs)) between fins on a substrate. In an example, fins are formed on a substrate. A liner layer is conformally formed on and between the fins. Forming the liner layer includes conformally depositing a pre-liner layer on and between the fins, and densifying, using a plasma treatment, the pre-liner layer to form the liner layer. A dielectric material is formed on the liner layer.
    Type: Application
    Filed: September 23, 2019
    Publication date: May 21, 2020
    Inventors: Benjamin COLOMBEAU, Theresa Kramer GUARINI, Malcolm BEVAN, Rui CHENG
  • Publication number: 20200144060
    Abstract: Methods for selective silicon film deposition on a substrate comprising a first surface and a second surface are described. More specifically, the process of depositing a film, treating the film to change some film property and selectively etching the film from various surfaces of the substrate are described. The deposition, treatment and etching can be repeated to selectively deposit a film on one of the two substrate surfaces.
    Type: Application
    Filed: June 6, 2018
    Publication date: May 7, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Rui Cheng, Fei Wang, Abhijit Basu Mallick, Robert Jan Visser
  • Patent number: 10636669
    Abstract: Aspects of the disclosure include methods of processing a substrate. The method includes depositing a conformal layer on a substrate which contains seams. The substrate is treated using a high pressure anneal in the presence of an oxidizer.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: April 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yihong Chen, Rui Cheng, Pramit Manna, Abhijit Basu Mallick, Shishi Jiang, Yong Wu, Kurtis Leschkies, Srinivas Gandikota
  • Patent number: 10626495
    Abstract: Methods for gapfill of high aspect ratio features are described. A first film is deposited on the bottom and upper sidewalls of a feature. The first film is etched from the sidewalls of the feature and the first film in the bottom of the feature is treated to form a second film. The deposition, etch and treat processes are repeated to fill the feature.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: April 21, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Rui Cheng, Abhijit Basu Mallick, Pramit Manna
  • Patent number: 10615050
    Abstract: Methods for seam-less gapfill comprising depositing a film in a feature, treating the film to change some film property and selectively etching the film from the top surface are described. The deposition, treatment and etching are repeated to form a seam-less gapfill in the feature.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 7, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Rui Cheng, Abhijit Basu Mallick, Pramit Manna, Yihong Chen