Abstract: A semiconductor storage device includes an array region, which includes memory cell array blocks and is connected to a (k: k is a natural number)-number of data input/output lines. A (k+m: m is a natural number)-number of common internal data lines are provided in common to the memory cell array blocks. A (k+m+n: n is a natural number)-number of individual internal data lines are provided to each memory cell array block. An individual line connection circuit is configured to respectively connect a (k+m)-number of the (k+m+n)-number of individual internal data lines to the (k+m)-number of common internal data lines, in accordance with a first defect information signal. A common line connection circuit is configured to respectively connect a k-number of the (k+m)-number of common internal data lines to the k-number of data input/output lines, in accordance with a second defect information signal.

Abstract: Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.

Abstract: A semiconductor memory device comprising a plurality of memory cells to store data, k data input/output lines (k=a natural number), a plurality of sense amplifiers which are provided in n number (n=a natural number) for the k data input/output lines, and perform reading and writing cell data for the plurality of memory cells, a column selection gate which selects one sense amplifier among the n sense amplifiers, and connects the selected sense amplifier to the corresponding data input/output line, a selector circuit which controls the column selection gate, and sequentially selects m sense amplifiers (m=1, 2, . . . , n) among the n sense amplifiers, and a switching circuit which changes the order of selecting the m sense amplifiers by the selector circuit.

Abstract: A semiconductor device has a least one logic circuit and at least one memory macro cell having a plurality of memory cell array blocks each composed of a plurality of memory cells. Addresses for designating the memory cell array blocks in test are selected among external addresses by a switching signal. The semiconductor device may have a plurality of memory macro cells having a plurality of memory cell array blocks each composed of a plurality of memory cells. The memory macro cells are switched in configuration as having the same length of rows or columns between the memory macro cells in test. The configuration is different from a configuration of row and column for a regular operation.

Abstract: A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.

Abstract: A plurality of memory macros are laid out in a semiconductor chip. Macro ID generation circuits generate macro IDs for identifying the memory macros, and have different layouts. These macro ID generation circuits are arranged outside the memory macros in the semiconductor chip, so that test control blocks in the memory macros can use the same layouts between all the memory macros to reduce the design load.

Abstract: Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.

Abstract: Disclosed is a semiconductor memory device comprising a memory circuit including an array of regular memory cells and an array of redundancy memory cells, a memory element including nonvolatile elements for storing unrewritable data that can be stored from outside, a register for holding the data of the memory element before the activation of the memory device, a redundancy determining circuit for comparing the data held in the register and the externally input address and determining the use or non-use of any of the redundancy memory cells and a redundancy data rewriting circuit adapted to receive a redundancy data from a source other than the memory element and input it to the register to use the redundancy data for rewriting.

Abstract: Disclosed is a semiconductor memory device comprising a memory circuit including an array of regular memory cells and an array of redundancy memory cells, a memory element including nonvolatile elements for storing unrewritable data that can be stored from outside, a register for holding the data of the memory element before the activation of the memory device, a redundancy determining circuit for comparing the data held in the register and the externally input address and determining the use or non-use of any of the redundancy memory cells and a redundancy data rewriting circuit adapted to receive a redundancy data from a source other than the memory element and input it to the register to use the redundancy data for rewriting.

Abstract: There is provided a memory-embedded semiconductor integrated circuit device capable of being tested in a shorter test time. The memory-embedded semiconductor integrated circuit device includes: a logic part provided on a semiconductor substrate; a memory macro provided on the semiconductor substrate to be consolidated with the logic part; a test input terminal for inputting a test input signal; a test circuit including a test signal generator for generating an output switching signal and a test signal, which serves to carry out a test operation of the memory macro, on the basis of the test input signal, and a switching circuit for selectively outputting one of an output of the memory macro, which has been test-operated by the test signal, and the test input signal in accordance with the output switching signal; and a test output terminal for receiving an output of the switching circuit to output the output of the switching circuit to the outside.

Abstract: In a semiconductor memory device having a redundant cell array, a replacement control circuit stores in advance a faulty address in an address space assigned to the memory cell array and information for specifying the dimension of the faulty address, compares each of external addresses XA and YA with the stored faulty address, and detects their coincidence. When the external address coincides with the faulty address, a redundant row or a redundant column constituting the redundant cell array is selected and replaced with the faulty cell, on the basis of the information representing the dimension of the faulty address. By this operation, the faulty cell on the memory cell array can be flexibly relieved, and the flexibility of redundancy can be improved.

Abstract: In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

Abstract: A semiconductor memory device including a memory cell array having memory cells arranged in XY directions, means for storing at least X addresses of failure bit memory cells among memory cells defined by an X address and a Y address in the memory cell array, and address means for generating an address Xe+m (m=positive or negative integer), serving as an internal address, when X address Xe corresponding to the failure bit address is inputted from an external section.

Abstract: A semiconductor memory device includes a series of memory cells, a series of bit lines respectively connected to the memory cells, a series of sense amplifiers, connected to corresponding bit line groups including predetermined number of bit lines of the series of bit lines, for reading out data of memory cells connected to bit lines of the bit line group, the bit line groups including at least adjacent first and second bit line groups, at least first and second transistors allocated between the bit lines and the sense amplifiers and having gates, for selectively connecting the bit lines and the sense amplifiers, and a series of control signal lines commonly connected to the first transistors connected to the first bit line groups and the second transistors connected to the second bit line groups, such that the first transistors connected to the first bit line groups are regularly arranged in one direction, and second transistors connected to the second bit line groups adjacent to the first bit line groups ar