Abstract: According to the semiconductor memory device of the embodiment, in the sense amplifier for the FBC, a first node and a second node can be disconnected from each other by a first isolation transistor. A third node and a fourth node can be disconnected from each other by a second isolation transistor. The first node is connected to the first memory cell. The third node is connected to the second memory cell. A first amplification transistor and a second amplification transistor are connected between the first node and the third node. A third amplification transistor and a fourth amplification transistor are connected between the second node and the fourth node. This enables to parallelly execute read data transfer to the data lines and precharge to prepare for the next read operation.

Abstract: A semiconductor memory device operating using initialization data, includes a first latch circuit which latches the initialization data, a memory cell array including a plurality of memory cells and having a first region and a second region, the first region storing data, and a buffer circuit having a function for accessing the first latch circuit, the buffer circuit transferring, to the second region, the initialization data transferred from the first latch circuit, and transferring, to the first latch circuit, the initialization data transferred form the second region.

Abstract: There is here disclosed a semiconductor integrated circuit comprising a laser beam irradiation object having one end portion at which a first potential is applied, a first transistor has a source and a drain wherein one of the source and the drain to which the other end portion of the object is electrically connected, a second transistor has a source and a drain wherein one of the source and the drain of the first transistor to which the other end portion is not electrically connected is electrically connected, and a storage circuit which is electrically connected to the one of the source and the drain of the second transistor to which the first transistor is electrically connected, and which is additionally electrically connected to the one of the source and the drain of the first transistor to which the other end portion is not electrically connected.

Abstract: A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer.

Abstract: A semiconductor integrated circuit device according to an embodiment of the present invention includes: a semiconductor substrate; an internal circuit formed on the semiconductor substrate, a first potential and a second potential being supplied to the internal circuit, thereby applying an operating voltage to the internal circuit; a fuse disposed above a semiconductor region of a first conductivity type, and electrically connected to the internal circuit, the semiconductor region being supplied with the second potential and being formed in the semiconductor substrate; and a protective element formed in the semiconductor region of the first conductivity type and protecting the internal circuit in response to positive and negative abnormal voltages generated in a wiring through which the fuse and the internal circuit are connected to each other.

Abstract: A semiconductor memory device operating using initialization data, includes a first latch circuit which latches the initialization data, a memory cell array including a plurality of memory cells and having a first region and a second region, the first region storing data, and a buffer circuit having a function for accessing the first latch circuit, the buffer circuit transferring, to the second region, the initialization data transferred from the first latch circuit, and transferring, to the first latch circuit, the initialization data transferred form the second region.

Abstract: A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.

Abstract: A semiconductor device has a least one logic circuit and at least one memory macro cell having a plurality of memory cell array blocks each composed of a plurality of memory cells. Addresses for designating the memory cell array blocks in test are selected among external addresses by a switching signal. The semiconductor device may have a plurality of memory macro calls having a plurality of memory cell array blocks each composed of a plurality of memory cells. The memory macro cells are switched in configuration as having the same length of rows or columns between the memory macro cells in test. The configuration is different from a configuration of row and column for a regular operation.

Abstract: A semiconductor integrated circuit apparatus, comprising a data transmitter circuit, and a plurality of data receiver circuits each having a data converter circuit which restores each of bits of identification number data and transfer data from a shift register of the data transmitter circuit to 2-bit complementary data transmitted via first and second transmission lines, a reception control circuit which, when a transfer completion signal has been received via a third transmission line, compares an allocated identification number with the restored identification number data, and a shift register provided in association with the reception control circuit, wherein each reception control circuit feeds transfer data transmitted from the data transmitter circuit corresponding to the identification number data to the associated shift register in accordance with a result of comparison between the identification number data and the allocated identification number.

Abstract: A semiconductor integrated circuit device includes a plurality of memory macros, macro-common register block, and memory macro operation setting circuits. The macro-common register block has macro-common registers which are provided outside the plurality of memory macros and supply memory macro operation specifying signals to the plurality of memory macros. The memory macro operation setting circuits are respectively provided in the plurality of memory macros and are each configured to set an operating state of the memory macro in response to the memory macro operation specifying signal supplied from the macro-common register.

Abstract: A semiconductor memory device includes a fuse element including a first terminal and a second terminal, which stores data based on whether or not it is electrically blown by a laser beam, a resistance element connected to the first terminal, a node in which the data is transferred, and a transistor provided between the resistance element and the node, which sets the data to the node.

Abstract: Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent registers in sequence. The plurality of first and second registers are connected in one-to-one correspondence to a plurality of input terminals or to a plurality of output terminals. A first scan input terminal is formed at one end of the plurality of first series-connected registers, and a first scan output terminal is formed at the other end. A second scan input terminal is formed at one end of the plurality of second series-connected registers, and a second scan output terminal is formed at the other end. An operation control circuit controls operations of the circuits and the plurality of first and second registers.

Abstract: There is here disclosed a semiconductor integrated circuit comprising a laser beam irradiation object having one end portion at which a first potential is applied, a first transistor has a source and a drain wherein one of the source and the drain to which the other end portion of the object is electrically connected, a second transistor has a source and a drain wherein one of the source and the drain of the first transistor to which the other end portion is not electrically connected is electrically connected, and a storage circuit which is electrically connected to the one of the source and the drain of the second transistor to which the first transistor is electrically connected, and which is additionally electrically connected to the one of the source and the drain of the first transistor to which the other end portion is not electrically connected.

Abstract: A semiconductor device transfers first data to a circuit block. The semiconductor device is provided with a storage circuit configured to store the first data, a shift register configured to set the first data, a transfer circuit configured to transfer the first data from the shift register to the circuit block, a first input terminal configured to receive a first signal indicating the end of a transfer operation, a resetting signal-generating circuit configured to generate a resetting signal for resetting the shift register based on the first signal, a setting signal-generating circuit configured to generate a setting signal for setting the first data in the shift register again after the shift register is reset, and an output circuit configured to externally output the first data that has been set again.

Abstract: A semiconductor memory device comprises a memory core, data control circuit, flag register, data register and computation circuit. The memory core has a plurality of memory cells for storing data. The data control circuit writes and reads first test data to and from the memory cells in synchrony with a clock signal. The flag register stores a plurality of flag data items. The data register stores second test data input corresponding to input of a command. The computation circuit performs, at every cycle, computation of the second test data, stored in the data register, and each of the flag data items stored in the flag register, thereby generating the first test data, until an n-th (n is a positive integer) cycle of the clock signal is reached. The first test data is written to the memory cells by the data control circuit.

Abstract: A semiconductor memory device includes a data line shift circuit, a plurality of data mask lines connected to the plurality of sense amplifier write circuits, respectively, and a plurality of mask circuits. The plurality of mask circuits each include at least one shift switch circuit and supply a mask signal to a sense amplifier write circuit, which is connected to a mask circuit different from that before a data line is shifted by the data line shift circuit, through the shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to the same mask circuit as that before the data line is shifted, not through the shift switch circuit.

Abstract: A semiconductor memory device includes a data line shift circuit, a plurality of data mask lines connected to the plurality of sense amplifier write circuits, respectively, and a plurality of mask circuits. The plurality of mask circuits each include at least one shift switch circuit and supply a mask signal to a sense amplifier write circuit, which is connected to a mask circuit different from that before a data line is shifted by the data line shift circuit, through the shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to the same mask circuit as that before the data line is shifted, not through the shift switch circuit.

Abstract: A semiconductor memory device includes a data line shift circuit, a plurality of data mask lines connected to the plurality of sense amplifier write circuits, respectively, and a plurality of mask circuits. The plurality of mask circuits each include at least one shift switch circuit and supply a mask signal to a sense amplifier write circuit, which is connected to a mask circuit different from that before a data line is shifted by the data line shift circuit, through the shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to the same mask circuit as that before the data line is shifted, not through the shift switch circuit.

Abstract: A semiconductor storage device includes an array region, which includes memory cell array blocks and is connected to a (k: k is a natural number)-number of data input/output lines. A (k+m: m is a natural number)-number of common internal data lines are provided in common to the memory cell array blocks. A (k+m+n: n is a natural number)-number of individual internal data lines are provided to each memory cell array block. An individual line connection circuit is configured to respectively connect a (k+m)-number of the (k+m+n)-number of individual internal data lines to the (k+m)-number of common internal data lines, in accordance with a first defect information signal. A common line connection circuit is configured to respectively connect a k-number of the (k+m)-number of common internal data lines to the k-number of data input/output lines, in accordance with a second defect information signal.

Abstract: A semiconductor memory device includes a data line shift circuit, a plurality of data mask lines connected to the plurality of sense amplifier write circuits, respectively, and a plurality of mask circuits. The plurality of mask circuits each include at least one shift switch circuit and supply a mask signal to a sense amplifier write circuit, which is connected to a mask circuit different from that before a data line is shifted by the data line shift circuit, through the shift switch circuit and supply the mask signal to a sense amplifier write circuit, which is connected to the same mask circuit as that before the data line is shifted, not through the shift switch circuit.