Patents by Inventor Ryo Fukuda
Ryo Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210082525Abstract: A semiconductor device includes pads for inputting and outputting data, a plurality of control circuit groups connected to the pads, a first supply line for supplying a first electric potential to the control circuit groups, and a second supply line for supplying a second electric potential lower than the first electric potential to the control circuit groups. At least one of the first electric potential supply line or the second supply line is provided with a blocking region such that the blocking region prevents supply of the first electric potential, and the first electric potential is supplied to the plurality of control circuit groups from the first supply line divided by the blocking region, or the blocking region prevents supply of the second electric potential, and the second electric potential is supplied to the plurality of control circuit groups from the second supply line divided by the blocking region.Type: ApplicationFiled: March 3, 2020Publication date: March 18, 2021Applicant: KIOXIA CORPORATIONInventors: Yasuhiro SUEMATSU, Masaru KOYANAGI, Kensuke YAMAMOTO, Ryo FUKUDA
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Publication number: 20210054545Abstract: Provided is a high-density medical fabric that can be suitably used as a graft for a branched stent graft, can accommodate diameter changes, has the burst strength required of a material to be implanted in a body, and has a seamless tubular shape that can narrow in diameter.Type: ApplicationFiled: December 12, 2018Publication date: February 25, 2021Applicant: Asahi Kasei Kabushiki KaishaInventors: Tokio Okuno, Ryo Fukuda
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Patent number: 9230653Abstract: According to an embodiment, a semiconductor device includes an IO terminal unit, an first IO line, and a second IO line. The IO terminal unit includes first and second IO terminals. The first IO line is electrically connected to one of both the first IO terminal and the second IO terminal. The second IO line is electrically connected to the other of both the first IO terminal and the second IO terminal. When the semiconductor device receives a first signal, the first IO terminal is electrically connected to the first IO line and the second IO terminal is electrically connected to the second IO line. When the semiconductor device receives a second signal, the first IO terminal is electrically connected to the second IO line and the second IO terminal is electrically connected to the first IO line. The second signal is different from the first signal.Type: GrantFiled: March 12, 2014Date of Patent: January 5, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Ryo Fukuda
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Patent number: 9218882Abstract: A nonvolatile semiconductor memory device includes a first memory string including memory cell transistors and a first select transistor that are connected in series, a second memory string including memory cell transistors and a second select transistor that are connected in series, a bit line that is electrically connected to a first end of the first memory string and a first end of the second memory string, a first transistor having a gate that is connected to a second end of the first memory string, a source line that is electrically connected to a first end of the first transistor, and a second transistor having a gate that is connected to a second end of the second memory string, a first end that is electrically connected to a second end of the first transistor, and a second end that is electrically connected to the bit line.Type: GrantFiled: September 2, 2014Date of Patent: December 22, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Ryo Fukuda
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Publication number: 20150262672Abstract: A nonvolatile semiconductor memory device includes a first memory string including memory cell transistors and a first select transistor that are connected in series, a second memory string including memory cell transistors and a second select transistor that are connected in series, a bit line that is electrically connected to a first end of the first memory string and a first end of the second memory string, a first transistor having a gate that is connected to a second end of the first memory string, a source line that is electrically connected to a first end of the first transistor, and a second transistor having a gate that is connected to a second end of the second memory string, a first end that is electrically connected to a second end of the first transistor, and a second end that is electrically connected to the bit line.Type: ApplicationFiled: September 2, 2014Publication date: September 17, 2015Inventor: Ryo FUKUDA
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Publication number: 20150070990Abstract: According to an embodiment, a semiconductor device includes an IO terminal unit, an first IO line, and a second IO line. The IO terminal unit includes first and second IO terminals. The first IO line is electrically connected to one of both the first IO terminal and the second IO terminal. The second IO line is electrically connected to the other of both the first IO terminal and the second IO terminal. When the semiconductor device receives a first signal, the first IO terminal is electrically connected to the first IO line and the second IO terminal is electrically connected to the second IO line. When the semiconductor device receives a second signal, the first IO terminal is electrically connected to the second IO line and the second IO terminal is electrically connected to the first IO line. The second signal is different from the first signal.Type: ApplicationFiled: March 12, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Ryo FUKUDA
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Patent number: 8811079Abstract: A volatile memory area includes a plurality of second memory cells, a third select transistor, and a fourth select transistor. The plurality of second memory cells are electrically connected in series, and stacked above the substrate. The third select transistor is connected to one end of the plurality of second memory cells, and connected to a second bit line. The fourth select transistor is connected to the other end of the plurality of second memory cells, and unconnected to a second source line. A controller is configured to supply a first voltage to all gates of the second memory cells. The first voltage is capable of turning on the plurality of second memory cells.Type: GrantFiled: January 29, 2013Date of Patent: August 19, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Ryo Fukuda, Daisaburo Takashima
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Patent number: 8736311Abstract: A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.Type: GrantFiled: March 7, 2013Date of Patent: May 27, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Ryo Fukuda, Masaru Koyanagi
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Publication number: 20140070295Abstract: A semiconductor memory device includes a capacitor. The capacitor includes: a first conductive layer functioning as a first electrode, the first conductive layer including a first portion; a second conductive layer functioning as the first electrode, the second conductive layer including a second portion, the second portion and the first portion being arranged in a first direction parallel to the semiconductor substrate; a third conductive layer functioning as a second electrode, the third conductive layer including a third portion; and a fourth conductive layer functioning as the second electrode, the fourth conductive layer including a fourth portion, the fourth portion and the third portion being arranged in the first direction, both the fourth portion and the third portion being arranged in a second direction away from the second portion and the first portion, the second direction being parallel to the semiconductor substrate and being orthogonal to the first direction.Type: ApplicationFiled: March 15, 2013Publication date: March 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryo FUKUDA, Takeshi Hioka, Hiroyasu Tanaka
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Publication number: 20140063963Abstract: According to one embodiment, a semiconductor memory device includes a memory core including a memory cell array, and a peripheral circuit configured to transfer data input to a pad unit to the memory core, and transfer data transferred from the memory core to the pad unit. The peripheral circuit includes a first region including a first data bus having a first wiring resistance, and a second region including a second data bus having a second wiring resistance lower than the first wiring resistance. The first region transfers data parallel at a first operating speed, and the second region serially transfers data at a second operating speed higher than the first operating speed.Type: ApplicationFiled: March 14, 2013Publication date: March 6, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Xu Li, Kiyotaro Itagaki, Ryo Fukuda
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Patent number: 8558602Abstract: According to one embodiment, a semiconductor integrated circuit includes first and second level shift circuits. The first level shifter includes a plurality of transistors and is connected to a power source voltage supply node of a first power source system and to which a first signal of a second power source system and a level inversion signal of the first signal are input. The second level shifter includes a plurality of transistors and is connected to the power source voltage supply node of the first power source system and to which the level inversion signal of the first signal of the second power source system and an output signal of the first level shifter are input. The first and second level shifters have substantially the same circuit configuration and driving abilities of corresponding ones of the transistors in the first and second level shifters are substantially set equal.Type: GrantFiled: September 17, 2010Date of Patent: October 15, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Ryo Fukuda, Masaru Koyanagi
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Patent number: 8502300Abstract: An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.Type: GrantFiled: September 14, 2011Date of Patent: August 6, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Ryo Fukuda, Yoshihisa Iwata
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Patent number: 8405432Abstract: An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.Type: GrantFiled: December 8, 2010Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Koyanagi, Yasufumi Kajiyama, Ryo Fukuda, Fumiyoshi Matsuoka, Yasuhiro Suematsu
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Patent number: 8405428Abstract: A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.Type: GrantFiled: May 2, 2011Date of Patent: March 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Ryo Fukuda, Masaru Koyanagi
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Patent number: 8258817Abstract: According to one embodiment, a semiconductor integrated circuit includes first to six transistors and a constant current source circuit. The first and second transistors form a current mirror circuit connected to a first power source node. The third and fourth transistors form a differential pair circuit. The third and fourth transistors receive first and second external signals at their gates, respectively. The constant current source circuit has one end connected to source terminals of the third and fourth transistors, and the other end connected to a second power source node. The fifth and sixth transistors form a current pathway between a common gate node of the first and second transistors and the constant current source circuit. The gate of fifth transistor is connected to a signal output node. The gate of sixth transistor receives a signal of logic opposite to a signal to be obtained at the signal output node.Type: GrantFiled: September 17, 2010Date of Patent: September 4, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Ryo Fukuda, Masaru Koyanagi
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Publication number: 20120182779Abstract: According to one embodiment, a nonvolatile memory device includes a substrate, an interconnect layer, a memory layer, a circuit layer, first and second contact interconnects. The interconnect layer is provided on the substrate and includes first and second interconnects. The memory layer is provided between the substrate and the interconnect layer and includes first and second memory cell array units. The first and second memory cell array units include a plurality of memory cells. The circuit layer is provided between the memory layer and the substrate and includes a first circuit unit. The first contact interconnect is provided between the first and second memory cell array units and electrically connects one end of the first circuit unit to the first interconnect. The second contact interconnect electrically connects a second end of the first circuit unit different from the first end to the second interconnect.Type: ApplicationFiled: January 17, 2012Publication date: July 19, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Ryo FUKUDA
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Publication number: 20120068256Abstract: An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.Type: ApplicationFiled: September 14, 2011Publication date: March 22, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryo Fukuda, Yoshihisa Iwata
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Publication number: 20110304377Abstract: A constant current source circuit includes one end connected to a second node as sources of third and fourth transistors, and the other end connected to a second power supply node that supplies a second voltage different from a first voltage. The clamp circuit is configured to form a current path between the second node and the second power supply node. It adjusts the potential of the second node to a certain potential when a first external input signal is switched from a first state to a second state.Type: ApplicationFiled: May 2, 2011Publication date: December 15, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Ryo FUKUDA, Masaru KOYANAGI
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Patent number: D839836Type: GrantFiled: December 19, 2017Date of Patent: February 5, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Ryo Fukuda, Kazuhide Uriu, Kohei Masuda
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Patent number: D865675Type: GrantFiled: December 19, 2017Date of Patent: November 5, 2019Assignee: Panasonic Intellectual Property Management Co., Lt Ltd.Inventors: Ryo Fukuda, Kazuhide Uriu, Kohei Masuda