Patents by Inventor Ryoichi Matsuoka

Ryoichi Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7518110
    Abstract: A pattern measuring method and device are provided which set a reference position for a measuring point to be measured by a scanning electron microscope and the like, based on position information of a reference pattern on an image acquired from the scanning electron microscope and based on a positional relation, detected by using design data, between the measuring point and the reference pattern formed at a position isolated from the measuring point.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: April 14, 2009
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takumichi Sutani, Ryoichi Matsuoka, Hidetoshi Morokuma, Hitoshi Komuro, Akiyuki Sugiyama
  • Patent number: 7507961
    Abstract: A pattern inspection apparatus can be provided, for example, in a scanning electron microscope system. When patterns of a plurality of layers are included in a SEM image, the apparatus separates the patterns according to each layer by using design data of the plurality of layers corresponding to the patterns. Consequently, the apparatus can realize inspection with use of only the pattern of a target layer to be inspected, pattern inspection differently for different layers, or detection of a positional offset between the layers.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: March 24, 2009
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yasutaka Toyoda, Akiyuki Sugiyama, Ryoichi Matsuoka, Takumichi Sutani, Hidemitsu Naya
  • Publication number: 20090052765
    Abstract: A pattern shape evaluation method and semiconductor inspection system having a unit for extracting contour data of a pattern from an image obtained by photographing a semiconductor pattern, a unit for generating pattern direction data from design data of the semiconductor pattern, and a unit for detecting a defect of a pattern, through comparison between pattern direction data obtained from the contour data and pattern direction data generated from the design data corresponding to a pattern position of the contour data.
    Type: Application
    Filed: August 15, 2008
    Publication date: February 26, 2009
    Inventors: Yasutaka TOYODA, Ryoichi MATSUOKA, Akiyuki SUGIYAMA
  • Publication number: 20090039263
    Abstract: Mutual compatibility is established between the measurement with a high magnification and the measurement in a wide region. A pattern measurement apparatus is proposed which adds identification information to each of fragments that constitute a pattern within an image obtained by the SEM, and which stores the identification information in a predetermined storage format. Here, the identification information is added to each fragment for distinguishing between one fragment and another fragment. According to the above-described configuration, it turns out that the identification information is added to each fragment on the SEM image which has possessed no specific identification information originally. As a result, it becomes possible to implement the SEM-image management based on the identification information.
    Type: Application
    Filed: August 8, 2008
    Publication date: February 12, 2009
    Inventors: Ryoichi MATSUOKA, Akihiro Onizawa, Akiyuki Sugiyama, Hidetoshi Morokuma, Yasutaka Toyoda
  • Publication number: 20090032707
    Abstract: Easily and correctly measuring a dimension of a pattern of a photomask or of an OPC pattern of the photomask. A pattern measurement method of the present invention includes steps of obtaining both a standard pattern corresponding to a predetermined pattern and a measurement point specified in advance; setting a measurement area so that it includes two straight line segments on both sides of the measurement point among outlines of the standard pattern; and measuring a dimension between two contours of the scanned image of the predetermined pattern in the measurement area by superposing the measurement area on the scanned image of the predetermined pattern. The measurement area is set so as not to include portions near corner portions connected to two line segments.
    Type: Application
    Filed: July 30, 2008
    Publication date: February 5, 2009
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Hidetoshi SATO, Ryoichi Matsuoka, Takumichi Sutani
  • Patent number: 7449689
    Abstract: The present invention relates to a dimension measuring SEM system and a circuit pattern evaluating system capable of achieving accurate, minute OPC evaluation, the importance of which increase with the progressive miniaturization of design pattern of a circuit pattern for a semiconductor device, and a circuit pattern evaluating method. Design data and measured data on an image of a resist pattern formed by photolithography are superposed for the minute evaluation of differences between a design pattern defined by the design data and the image of the resist pattern, and one- or two-dimensional geometrical features representing differences between the design pattern and the resist pattern are calculated. In some cases, the shape of the resist pattern differs greatly from the design pattern due to OPE effect (optical proximity effect).
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: November 11, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Wataru Nagatomo, Ryoichi Matsuoka, Takumichi Sutani, Akiyuki Sugiyama, Yasuhiro Yoshitake, Hideaki Sasazawa
  • Publication number: 20080224035
    Abstract: An evaluation method and apparatus is provided for evaluating a displacement between patterns of a pattern image by using design data representative of a plurality of patterns superimposed ideally. A first distance is measured for an upper layer pattern between a line segment of the design data and an edge of the charged particle radiation image, a second distance is measured for a lower layer pattern between a line segment of the design data and an edge of the charged particle radiation image; and an superimposition displacement is detected between the upper layer pattern and lower layer pattern in accordance with the first distance and second distance.
    Type: Application
    Filed: August 24, 2007
    Publication date: September 18, 2008
    Inventors: Takumichi Sutani, Ryoichi Matsuoka, Hidetoshi Morokuma, Akiyuki Sugiyama, Hiroyuki Shindo
  • Publication number: 20080175469
    Abstract: There is provided a pattern inspection apparatus that is capable of detecting a defect accurately and efficiently to inspect a pattern of a semiconductor device. The pattern inspection apparatus includes: a contour extraction means for extracting contour data of a pattern from a captured image of the semiconductor device; a non-linear part extraction means for extracting a non-linear part from the contour data; an angular part extraction means for extracting an angular part of a pattern from design data of the semiconductor device; and a defect detection section that compares a position of the non-linear part extracted by the non-linear part extraction section with a position of the angular part extracted by the angular part extraction section so as to detect a position of a defective part of a pattern.
    Type: Application
    Filed: August 6, 2007
    Publication date: July 24, 2008
    Applicant: Hitachi High-Technologies Corporation
    Inventors: Yasutaka TOYODA, Takumichi Sutani, Ryoichi Matsuoka, Hidemitsu Naya
  • Publication number: 20080159609
    Abstract: This invention relates to a SEM system constructed to create imaging recipes or/and measuring recipes automatically and at high speed, and improve inspection efficiency and an automation ratio, and to a method using the SEM system; a method for creation of imaging recipes and measuring recipes in the SEM system is adapted to include, in a recipe arithmetic unit, the steps of evaluating a tolerance for an imaging position error level at an evaluation point, evaluating a value predicted of the imaging position error level at the evaluation point when any region on circuit pattern design data is defined as an addressing point, and determining an imaging recipe and a measuring recipe on the basis of a relationship between the tolerance for the imaging position error level at the evaluation point and the predicted value of the imaging position error level at the evaluation point.
    Type: Application
    Filed: December 12, 2007
    Publication date: July 3, 2008
    Inventors: Atsushi Miyamoto, Tomofumi Nishiura, Ryoichi Matsuoka, Hidetoshi Morokuma
  • Patent number: 7365322
    Abstract: In order to provide an imaging-recipe arranging or creating apparatus and method adapted so that selection rules for automatic arrangement of an imaging recipe can be optimized by teaching in a SEM apparatus or the like, the imaging-recipe arranging or creating apparatus in this invention that arranges an imaging recipe for SEM-observing a semiconductor pattern using a scanning electron microscope includes a database that receives and stores layout information of the above semiconductor pattern in a low-magnification field, and an imaging-recipe arranging unit which, on the basis of the database-stored semiconductor pattern layout information, arranges the imaging recipe automatically in accordance with the automatic arrangement algorithm that includes teaching-optimized selection rules for selecting an imaging point(s).
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: April 29, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Miyamoto, Wataru Nagatomo, Ryoichi Matsuoka, Hidetoshi Morokuma, Takumichi Sutani
  • Publication number: 20080016481
    Abstract: A system and a method for detecting a defect, capable of extracting a defect occurring depending on finishing accuracy required for circuit operation are provided. The system includes a timing analyzer 412 for extracting a critical path in which a high accuracy is required for a signal transmission operation as compared with other portions based on circuit design data, a critical path extractor 413 for comparing the circuit design data with layout design data on a pattern and for extracting graphical data including the critical path extracted by the timing analyzer 412, an inspection recipe creator 416 for deciding a portion to be inspected, based on coordinate information on the graphical data including the critical path extracted by the critical path extractor 413, and an SEM defect review apparatus 300 for acquiring an image of the decided portion to be inspected on a wafer according to an inspection recipe created by the inspection recipe creator 416.
    Type: Application
    Filed: June 21, 2007
    Publication date: January 17, 2008
    Applicant: Hitachi High-Technologies Corp.
    Inventors: Ryoichi Matsuoka, Hidetoshi Morokuma, Takumichi Sutani
  • Publication number: 20070221842
    Abstract: A workpiece size measurement method suitable for length measurement of multilayered circuit elements with increased complexities is disclosed. This method employs a technique for changing measurement conditions in a way pursuant to either an image of workpiece or the situation of a target semiconductor circuit element to be measured when measuring pattern sizes on the workpiece image using design data of the semiconductor circuit element. With such an arrangement, adequate measurement conditions are selectable in accordance with the state of workpiece image and/or the state of a circuit element formed on the workpiece, thereby making it possible to improve the measurement efficiency. A workpiece size measurement apparatus using the technique is also disclosed.
    Type: Application
    Filed: March 14, 2007
    Publication date: September 27, 2007
    Inventors: Hidetoshi Morokuma, Takumichi Sutani, Ryoichi Matsuoka, Hitoshi Komuro, Akiyuki Sugiyama
  • Publication number: 20070210252
    Abstract: (1) part or all of the number, coordinates and size/shape and imaging sequence of imaging points each for observation, the imaging position change method and imaging conditions can be calculated automatically from CAD data, (2) a combination of input information and output information for imaging recipe creation can be set arbitrarily, and (3) decision is made of imaging or processing at an arbitrary imaging point as to whether to be successful/unsuccessful and in case a failure is determined, a relief process can be conducted in which the imaging point or imaging sequence is changed.
    Type: Application
    Filed: February 9, 2007
    Publication date: September 13, 2007
    Inventors: Atsushi MIYAMOTO, Wataru Nagatomo, Ryoichi Matsuoka, Hidetoshi Morokuma
  • Patent number: 7257785
    Abstract: An apparatus of evaluating a layer matching deviation based on CAD information of the invention, is provided with means for storing CAD data and a function of displaying to overlap a scanning microscope image of a pattern of a semiconductor device formed on a wafer and a design CAD image read from the storing means and a function of evaluating acceptability of formation of the pattern by displaying to overlap a pattern image of the semiconductor device formed on the wafer and the design CAD image of the pattern, in addition thereto, a function capable of evaluating acceptability of formation of the pattern also with regard to a shape and positional relationship with a pattern formed at a later step by displaying to overlap a design CAD image of the pattern formed at the later step.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: August 14, 2007
    Assignee: SII NanoTechnology Inc.
    Inventor: Ryoichi Matsuoka
  • Publication number: 20070120056
    Abstract: The present invention provides a semiconductor pattern shape evaluating apparatus using a critical dimension SEM, which eliminates the necessity of data conversion corresponding to each process of semiconductor manufacturing conventionally required; controls possessed data integratedly; can select data effective for use in each process from the possessed data easily; if the shape of formed pattern changes with time, can create a photographing recipe which enables stable measurement by correcting the photographing recipe based on time-series data. Specifically, the semiconductor pattern shape evaluating apparatus correlates coordinate systems among diversified data to control the diversified data stored in a database integratedly, selects part or all of the diversified data arbitrarily and creates a photographing recipe for observing a semiconductor pattern with a critical dimension SEM using selected data.
    Type: Application
    Filed: November 15, 2006
    Publication date: May 31, 2007
    Inventors: Wataru Nagatomo, Atsushi Miyamoto, Ryoichi Matsuoka
  • Publication number: 20070098248
    Abstract: Solving means is configured of a signal input interface, a data calculation unit, and a signal output interface. The signal input interface allows image data which is obtained by photographing hole patterns, and CAD data which corresponds to hole patterns included in the image data, to be inputted.
    Type: Application
    Filed: October 27, 2006
    Publication date: May 3, 2007
    Inventors: Yasutaka Toyoda, Takumichi Sutani, Ryoichi Matsuoka
  • Publication number: 20070023653
    Abstract: A pattern inspection apparatus can be provided, for example, in a scanning electron microscope system. When patterns of a plurality of layers are included in a SEM image, the apparatus separates the patterns according to each layer by using design data of the plurality of layers corresponding to the patterns. Consequently, the apparatus can realize inspection with use of only the pattern of a target layer to be inspected, pattern inspection differently for different layers, or detection of a positional offset between the layers.
    Type: Application
    Filed: June 15, 2006
    Publication date: February 1, 2007
    Inventors: Yasutaka Toyoda, Akiyuki Sugiyama, Ryoichi Matsuoka, Takumichi Sutani, Hidemitsu Naya
  • Publication number: 20060288325
    Abstract: In an imaging recipe creating apparatus that uses a scanning electron microscope to create an imaging recipe for SEM observation of a semiconductor pattern, in order that the imaging recipe for measuring the wiring width and other various dimension values of the pattern from an observation image and thus evaluating the shape of the pattern is automatically generated within a minimum time by the analysis using the CAD image obtained by conversion from CAD data, an CAD image creation unit that creates the CAD image by converting the CAD data into an image format includes an image-quantizing width determining section, a brightness information providing section, and a pattern shape deformation processing section; the imaging recipe being created using the CAD image created by the CAD image creation unit.
    Type: Application
    Filed: January 31, 2006
    Publication date: December 21, 2006
    Inventors: Atsushi Miyamoto, Wataru Nagatomo, Ryoichi Matsuoka, Hidetoshi Morokuma, Takumichi Sutani
  • Publication number: 20060284081
    Abstract: In order to provide an imaging-recipe arranging or creating apparatus and method adapted so that selection rules for automatic arrangement of an imaging recipe can be optimized by teaching in a SEM apparatus or the like, the imaging-recipe arranging or creating apparatus in this invention that arranges an imaging recipe for SEM-observing a semiconductor pattern using a scanning electron microscope includes a database that receives and stores layout information of the above semiconductor pattern in a low-magnification field, and an imaging-recipe arranging unit which, on the basis of the database-stored semiconductor pattern layout information, arranges the imaging recipe automatically in accordance with the automatic arrangement algorithm that includes teaching-optimized selection rules for selecting an imaging point(s).
    Type: Application
    Filed: January 12, 2006
    Publication date: December 21, 2006
    Inventors: Atsushi Miyamoto, Wataru Nagatomo, Ryoichi Matsuoka, Hidetoshi Morokuma, Takumichi Sutani
  • Publication number: 20060193508
    Abstract: A pattern measuring method and device are provided which set a reference position for a measuring point to be measured by a scanning electron microscope and the like, based on position information of a reference pattern on an image acquired from the scanning electron microscope and based on a positional relation, detected by using design data, between the measuring point and the reference pattern formed at a position isolated from the measuring point.
    Type: Application
    Filed: February 23, 2006
    Publication date: August 31, 2006
    Inventors: Takumichi Sutani, Ryoichi Matsuoka, Hidetoshi Morokuma, Hitoshi Komuro, Akiyuki Sugiyama