Patents by Inventor Ryu Hirota
Ryu Hirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10837124Abstract: A gallium nitride substrate has a surface with a diameter of not less than 100 mm, a difference being not less than 0.1 cm?1 and not more than 2 cm?1 between maximum and minimum values of wave numbers at a maximum peak of peaks corresponding to an E2H phonon mode in micro-Raman scattering mapping measurement at each of square regions having sides each having a length of 2 mm, the square regions being located at a total of five locations including a central location and four circumferential edge locations on the surface of the gallium nitride substrate, a difference being not more than 2 cm?1 between maximum and minimum values of the wave numbers at the maximum peak of the peaks corresponding to the E2H phonon mode at all of measurement points in the five locations.Type: GrantFiled: September 16, 2019Date of Patent: November 17, 2020Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Makoto Kiyama, Ryu Hirota, Seiji Nakahata
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Publication number: 20200032419Abstract: A gallium nitride substrate has a surface with a diameter of not less than 100 mm, a difference being not less than 0.1 cm?1 and not more than 2 cm?1 between maximum and minimum values of wave numbers at a maximum peak of peaks corresponding to an E2H phonon mode in micro-Raman scattering mapping measurement at each of square regions having sides each having a length of 2 mm, the square regions being located at a total of five locations including a central location and four circumferential edge locations on the surface of the gallium nitride substrate, a difference being not more than 2 cm?1 between maximum and minimum values of the wave numbers at the maximum peak of the peaks corresponding to the E2H phonon mode at all of measurement points in the five locations.Type: ApplicationFiled: September 16, 2019Publication date: January 30, 2020Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Makoto KIYAMA, Ryu HIROTA, Seiji NAKAHATA
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Patent number: 10458043Abstract: A gallium nitride substrate has a surface with a diameter of not less than 100 mm, a difference being not less than 0.1 cm?1 and not more than 2 cm?1 between maximum and minimum values of wave numbers at a maximum peak of peaks corresponding to an E2H phonon mode in micro-Raman scattering mapping measurement at each of square regions having sides each having a length of 2 mm, the square regions being located at a total of five locations including a central location and four circumferential edge locations on the surface of the gallium nitride substrate, a difference being not more than 2 cm?1 between maximum and minimum values of the wave numbers at the maximum peak of the peaks corresponding to the E2H phonon mode at all of measurement points in the five locations.Type: GrantFiled: April 10, 2015Date of Patent: October 29, 2019Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Makoto Kiyama, Ryu Hirota, Seiji Nakahata
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Patent number: 10443151Abstract: There is provided a gallium nitride substrate having a C plane as a surface with a diameter of not less than 100 mm, the gallium nitride substrate including first regions and second regions having different average values of band-edge emission intensities in a micro photoluminescence mapping at 25° C. in a square region located in the C plane and having sides each having a length of 2 mm, an average value Ibe1a of the band-edge emission intensities of the first regions and an average value Ibe2a of the band-edge emission intensities of the second regions satisfying the following relational expressions (I) and (II): Ibe1a>Ibe2a . . . (I) and 2.1?Ibe1a/Ibe2a?9.4 . . . (II).Type: GrantFiled: April 20, 2018Date of Patent: October 15, 2019Assignee: Sumitomo Electric Industries, Ltd.Inventors: Makoto Kiyama, Ryu Hirota, Seiji Nakahata
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Publication number: 20180237946Abstract: There is provided a gallium nitride substrate having a C plane as a surface with a diameter of not less than 100 mm, the gallium nitride substrate including first regions and second regions having different average values of band-edge emission intensities in a micro photoluminescence mapping at 25° C. in a square region located in the C plane and having sides each having a length of 2 mm, an average value Ibe1a of the band-edge emission intensities of the first regions and an average value Ibe2a of the band-edge emission intensities of the second regions satisfying the following relational expressions (I) and (II): Ibe1a>Ibe2a . . . (I) and 2.1?Ibe1a/Ibe2a?9.4 . . . (II).Type: ApplicationFiled: April 20, 2018Publication date: August 23, 2018Applicant: Sumitomo Electric Industries, Ltd.Inventors: Makoto KIYAMA, Ryu HIROTA, Seiji NAKAHATA
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Patent number: 10006147Abstract: There is provided a gallium nitride substrate having a C plane as a surface with a diameter of not less than 100 mm, the gallium nitride substrate including first regions and second regions having different average values of band-edge emission intensities in a micro photoluminescence mapping at 25° C. in a square region located in the C plane and having sides each having a length of 2 mm, an average value Ibe1a of the band-edge emission intensities of the first regions and an average value Ibe2a of the band-edge emission intensities of the second regions satisfying the following relational expressions (I) and (II): Ibe1a>Ibe2a??(I) and 2.1?Ibe1a/Ibe2a?9.4??(II).Type: GrantFiled: April 16, 2015Date of Patent: June 26, 2018Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Makoto Kiyama, Ryu Hirota, Seiji Nakahata
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Publication number: 20170137966Abstract: A gallium nitride substrate has a surface with a diameter of not less than 100 mm, a difference being not less than 0.1 cm?1 and not more than 2 cm?1 between maximum and minimum values of wave numbers at a maximum peak of peaks corresponding to an E2H phonon mode in micro-Raman scattering mapping measurement at each of square regions having sides each having a length of 2 mm, the square regions being located at a total of five locations including a central location and four circumferential edge locations on the surface of the gallium nitride substrate, a difference being not more than 2 cm?1 between maximum and minimum values of the wave numbers at the maximum peak of the peaks corresponding to the E2H phonon mode at all of measurement points in the five locations.Type: ApplicationFiled: April 10, 2015Publication date: May 18, 2017Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Makoto KIYAMA, Ryu HIROTA, Seiji NAKAHATA
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Publication number: 20170101724Abstract: There is provided a gallium nitride substrate having a C plane as a surface with a diameter of not less than 100 mm, the gallium nitride substrate including first regions and second regions having different average values of band-edge emission intensities in a micro photoluminescence mapping at 25° C. in a square region located in the C plane and having sides each having a length of 2 mm, an average value Ibe1a of the band-edge emission intensities of the first regions and an average value Ibe2a of the band-edge emission intensities of the second regions satisfying the following relational expressions (I) and (II): Ibe1a>Ibe2a . . . (I) and 2.1?Ibe1a/Ibe2a?9.4 . . . (II).Type: ApplicationFiled: April 16, 2015Publication date: April 13, 2017Applicant: Sumitomo Electric Industries, Ltd.Inventors: Makoto KIYAMA, Ryu HIROTA, Seiji NAKAHATA
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Publication number: 20130244406Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.Type: ApplicationFiled: February 26, 2013Publication date: September 19, 2013Applicant: Sumitomo Electric Industries, Ltd.Inventors: Hitoshi KASAI, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideyuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Patent number: 8404569Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.Type: GrantFiled: November 18, 2010Date of Patent: March 26, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hitoshi Kasai, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideyuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Patent number: 8310030Abstract: Affords methods of manufacturing bulk III-nitride crystals whereby at least the surface dislocation density is low globally. The present III-nitride crystal manufacturing method includes: a step of preparing an undersubstrate (1) containing a III-nitride seed crystal, the III-nitride seed crystal having a matrix (1s), and inversion domains (1t) in which the polarity in the <0001> directions is inverted with respect to the matrix (1s); and a step of growing a III-nitride crystal (10) onto the matrix (1s) and inversion domains (it) of the undersubstrate (1) by a liquid-phase technique; and is characterized in that a first region (10s), being where the growth rate of III-nitride crystal (10) growing onto the matrix (1s) is greater, covers second regions (10t), being where the growth rate of III-nitride crystal (10) growing onto the inversion domains (1t) is lesser.Type: GrantFiled: July 7, 2011Date of Patent: November 13, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Ryu Hirota, Koji Uematsu, Tomohiro Kawase
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Patent number: 8304334Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.Type: GrantFiled: February 7, 2012Date of Patent: November 6, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Patent number: 8198177Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1-x-yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: GrantFiled: October 25, 2011Date of Patent: June 12, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
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Publication number: 20120142168Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.Type: ApplicationFiled: February 7, 2012Publication date: June 7, 2012Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Patent number: 8134223Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.Type: GrantFiled: November 13, 2009Date of Patent: March 13, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Publication number: 20120040511Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1?x?yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: ApplicationFiled: October 25, 2011Publication date: February 16, 2012Applicant: Sumitomo Electric Industries, Ltd.Inventors: Seiji NAKAHATA, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
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Patent number: 8067300Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1-x-yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: GrantFiled: April 28, 2009Date of Patent: November 29, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
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Publication number: 20110260295Abstract: Affords methods of manufacturing bulk III-nitride crystals whereby at least the surface dislocation density is low globally. The present III-nitride crystal manufacturing method includes: a step of preparing an undersubstrate (1) containing a III-nitride seed crystal, the III-nitride seed crystal having a matrix (1s), and inversion domains (1t) in which the polarity in the <0001> directions is inverted with respect to the matrix (1s); and a step of growing a III-nitride crystal (10) onto the matrix (1s) and inversion domains (it) of the undersubstrate (1) by a liquid-phase technique; and is characterized in that a first region (10s), being where the growth rate of III-nitride crystal (10) growing onto the matrix (1s) is greater, covers second regions (10t), being where the growth rate of III-nitride crystal (10) growing onto the inversion domains (1t) is lesser.Type: ApplicationFiled: July 7, 2011Publication date: October 27, 2011Applicant: Sumitomo Electric Industries, Ltd.Inventors: Ryu Hirota, Koji Uematsu, Tomohiro Kawase
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Patent number: 8038794Abstract: A method of manufacturing a group III-nitride crystal substrate including the steps of introducing an alkali-metal-element-containing substance, a group III-element-containing substance and a nitrogen-element-containing substance into a reactor, forming a melt containing at least the alkali metal element, the group III-element and the nitrogen element in the reactor, and growing group III-nitride crystal from the melt, and characterized by handling the alkali-metal-element-containing substance in a drying container in which moisture concentration is controlled to at most 1.0 ppm at least in the step of introducing the alkali-metal-element-containing substance into the reactor is provided. A group III-nitride crystal substrate attaining a small absorption coefficient and the method of manufacturing the same, as well as a group III-nitride semiconductor device can thus be provided.Type: GrantFiled: April 15, 2005Date of Patent: October 18, 2011Assignees: Sumitomo Electric Industries, Ltd.Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Seiji Nakahata, Ryu Hirota
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Patent number: 8002892Abstract: Affords a Group-III nitride crystal substrate that is of low dislocation density and is inexpensive to manufacture, a method of manufacturing such a substrate, and Group-III nitride semiconductor devices that incorporate the Group-III nitride crystal substrate. The Group-III nitride crystal substrate manufacturing method includes: a step of growing, by liquid-phase epitaxy, a first Group-III nitride crystal (2) onto a base substrate (1); and a step of growing, by vapor-phase epitaxy, a second Group-III nitride crystal (3) onto the first Group-III nitride crystal (2). The Group-III nitride crystal substrate, produced by such a manufacturing method, has a dislocation density of 1×107 dislocations/cm2.Type: GrantFiled: January 24, 2005Date of Patent: August 23, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Ryu Hirota, Seiji Nakahata, Masaki Ueno