Patents by Inventor Ryu Hirota
Ryu Hirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7105865Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1-x-yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: GrantFiled: January 25, 2005Date of Patent: September 12, 2006Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
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Patent number: 7087114Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: October 8, 2002Date of Patent: August 8, 2006Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Publication number: 20060012011Abstract: A method of processing a surface of a nitride semiconductor crystal, wherein a surface of a nitride semiconductor crystal is brought into contact with a liquid containing at least Na, Li or Ca as a processing solution. In the method, the processing solution can be a liquid containing at least Na, having an Na content of 5-95 mol %. The processing solution can be a liquid containing at least Li, having an Li content of 5-100 mol %. A nitride semiconductor crystal having a maximum depth of a surface scratch of at most 0.01 ?m or an average thickness of a damaged layer of at most 2 ?m. Consequently, a method of processing a surface of a nitride semiconductor crystal with a decreased depth of a surface scratch or a decreased thickness of a damaged layer, and a nitride semiconductor crystal obtained with the method can be provided.Type: ApplicationFiled: June 3, 2004Publication date: January 19, 2006Inventors: Seiji Nakahata, Ryu Hirota, Keiji Ishibashi, Takatomo Sasaki, Yusuke Mori
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Publication number: 20050242357Abstract: Affords semiconductor light-emitting devices in which generation of spontaneous electric fields in the active layer is reduced to enable enhanced brightness. Semiconductor light-emitting device (1) is furnished with an n-type cladding layer (3), a p-type cladding layer (7) provided over the n-type cladding layer (3), and an active layer (5) composed of a nitride and provided in between the n-type cladding layer (3) and the p-type cladding layer (7), and therein is characterized in that the angle formed by an axis orthogonal to the interface between the n-type cladding layer (3) and the active layer (5), and the c-axis in the active layer (5), and the angle formed by an axis orthogonal to the interface between the active layer (5) and the p-type cladding layer (7), and the c-axis in the active layer (5), are each greater than zero.Type: ApplicationFiled: April 28, 2005Publication date: November 3, 2005Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Koji Uematsu, Masaki Ueno, Ryu Hirota, Hideaki Nakahata, Manabu Okui
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Publication number: 20050227472Abstract: A method of manufacturing a group III-V crystal is made available by which good-quality group III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. A method of manufacturing a group III-V crystal, characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2) in an atmosphere in which a patterning compound is present; and a step of growing a group III-V crystal (4) on the metal film after the heat treatment. Additionally, a method of manufacturing a group III-V crystal, characterized in including: a step of growing a group III-V compound buffer film on the metal film after the heat treatment; and a step of growing a group III-V crystal on the group III-V compound buffer film.Type: ApplicationFiled: April 1, 2004Publication date: October 13, 2005Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Publication number: 20050183658Abstract: A low dislocation density AlxInyGa1-x-yN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing an AlxInyGa1-x-yN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: ApplicationFiled: March 1, 2005Publication date: August 25, 2005Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Koji Uematsu
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Publication number: 20050164419Abstract: Affords a Group-III nitride crystal substrate that is of low dislocation density and is inexpensive to manufacture, a method of manufacturing such a substrate, and Group-III nitride semiconductor devices that incorporate the Group-III nitride crystal substrate. The Group-III nitride crystal substrate manufacturing method includes: a step of growing, by liquid-phase epitaxy, a first Group-III nitride crystal (2) onto a base substrate (1); and a step of growing, by vapor-phase epitaxy, a second Group-III nitride crystal (3) onto the first Group-III nitride crystal (2). The Group-III nitride crystal substrate, produced by such a manufacturing method, has a dislocation density of 1×107 dislocations/cm2.Type: ApplicationFiled: January 24, 2005Publication date: July 28, 2005Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Ryu Hirota, Seiji Nakahata, Masaki Ueno
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Publication number: 20050161697Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1-x-yN (0?×?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: ApplicationFiled: January 25, 2005Publication date: July 28, 2005Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
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Publication number: 20050153471Abstract: There is provided a method of manufacturing a group-III nitride crystal in which a nitrogen plasma is brought into contact with a melt containing a group-III element and an alkali metal to grow the group-III nitride crystal. Furthermore, there is also provided a method of manufacturing a group-III nitride crystal in which the group-III nitride crystal is grown on a substrate placed in a melt containing a group-III element and an alkali metal, with a minimal distance between a surface of the melt and a surface of the substrate set to be at most 50 mm.Type: ApplicationFiled: November 29, 2004Publication date: July 14, 2005Applicants: Sumitomo Electric Industries, Ltd., Yusuke MORIInventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Ryu Hirota
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Publication number: 20050098090Abstract: Affords Group III nitride crystals whose crystal growth rate is extensive, methods of their manufacture, and equipment for manufacturing such Group III nitride crystals. The manufacturing methods include: a melt-formation step, within a reaction vessel (21), of forming around a seed crystal (2) a melt (1) containing at least a Group III element and a catalyst; and a crystal-growth step of supplying a nitrogen-containing substance (3) to the melt (1) to grow a Group III nitride crystal (4) onto the seed crystal (2); characterized in controlling temperature so that in the crystal-growth step, the temperature of the melt (1) lowers from the interface (13) between the melt (1) and the nitrogen-containing substance (3), through to the interface (12) between the melt (1) and the seed crystal (2) or to the interface (14) between the melt (1) and the Group III nitride crystal (4) having grown onto the seed crystal (2).Type: ApplicationFiled: November 1, 2004Publication date: May 12, 2005Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Ryu Hirota, Seiji Nakahata
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Publication number: 20050092234Abstract: Dotted seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations from neighboring regions, accumulate the dislocations into pit bottoms, and make closed defect accumulating regions (H) on the seeds. The polycrystalline or slanting orientation single crystal closed defect accumulating regions (H) induce microcracks due to thermal expansion anisotropy. The best one is orientation-inversion single crystal closed defect accumulating regions (H). At an early stage, orientation-inverse protrusions are induced on tall facets and unified with each other above the seeds. Orientation-inverse crystals growing on the unified protrusions become the orientation-inverse single crystal closed defect accumulating regions (H).Type: ApplicationFiled: September 3, 2004Publication date: May 5, 2005Inventors: Kensaku Motoki, Takuji Okahisa, Ryu Hirota, Seiji Nakahata, Koji Uematsu
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Publication number: 20050076830Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: ApplicationFiled: September 9, 2004Publication date: April 14, 2005Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Publication number: 20040089919Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: ApplicationFiled: November 5, 2003Publication date: May 13, 2004Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kensaku Motoki, Takuji Okahisa, Seiji Nakahata, Ryu Hirota, Koji Uematsu
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Patent number: 6667184Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: GrantFiled: September 19, 2002Date of Patent: December 23, 2003Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Takuji Okahisa, Seiji Nakahata, Ryu Hirota, Koji Uematsu
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Publication number: 20030145783Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: ApplicationFiled: October 8, 2002Publication date: August 7, 2003Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Publication number: 20030080345Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: ApplicationFiled: September 19, 2002Publication date: May 1, 2003Applicant: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Takuji Okahisa, Seiji Nakahata, Ryu Hirota, Koji Uematsu
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Patent number: 6475277Abstract: A vapor phase growth apparatus 1 for growing a group III-V nitride semiconductor (GaN) comprises a reaction ampoule 3 having a container 11 disposed therein for containing a group III element and an inlet 7 for introducing nitrogen; excitation means 15 for plasma-exciting nitrogen introduced from the inlet 7; and heating means 13 for heating a seed crystal 10 disposed within the reaction ampoule 3 and the container 11; wherein, upon growing the group III-V nitride semiconductor on the seed crystal 10, nitrogen is introduced from the inlet 7, and no gas is let out from within the reaction ampoule 3.Type: GrantFiled: June 29, 2000Date of Patent: November 5, 2002Assignee: Sumitomo Electric Industries, Ltd.Inventors: Ryu Hirota, Masami Tatsumi
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Patent number: 6132506Abstract: An object of the present invention is to provide a method for the heat treatment of ZnSe crystal whereby the crystal can be prevented from deterioration of crystallinity and caused to have low resistivity without occurrence of precipitates in the crystal. The feature of the present invention consists in a method for the heat treatment of ZnSe comprising subjecting ZnSe crystal grown by a chemical vapor transport method using iodine as a transport agent to a heat treatment in a Zn vapor atmosphere and controlling a cooling rate after the heat treatment in 10 to 200.degree. C./min.Type: GrantFiled: June 18, 1999Date of Patent: October 17, 2000Assignee: Sumitomo Electric Industries, Ltd.Inventors: Ryu Hirota, Shinsuke Fujiwara
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Patent number: 5944891Abstract: An object of the present invention is to provide a method for the heat treatment of a ZnSe crystal whereby the crystal can be prevented from crystallinity deterioration and caused to have low resistivity without occurrence of precipitates in the crystal.The feature of the present invention consists in a method for the heat treatment of ZnSe comprising subjecting ZnSe crystal grown by a chemical vapor transport method using iodine as a transport agent to a heat treatment in a Zn vapor atmosphere and controlling a cooling rate after the heat treatment in 10 to 200.degree. C./min.Type: GrantFiled: August 11, 1997Date of Patent: August 31, 1999Assignee: Sumitomo Electric Industries, Ltd.Inventors: Ryu Hirota, Shinsuke Fujiwara
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Patent number: 5933751Abstract: An object of the invention is to provide a method for the heat treatment of II-VI semiconductors such as ZnS, ZnS.sub.x Se.sub.1-x, Zn.sub.y Cd.sub.1-y Se, etc. to dope with Group III elements as a donor impurity to reduce its resistivity. This object can be attained by a method for the heat treatment of II-VI semiconductors in a closed vessel, which comprises forming a film of a Group III element as a donor impurity or a Group III element-containing compound on a surface of single crystal of II-VI semiconductors, then charging the single crystal and a Group II element for constituting the single crystal in the closed vessel and heating them in such a manner that the both are not contacted with each other.Type: GrantFiled: January 23, 1998Date of Patent: August 3, 1999Assignee: Sumitomo Electric Industries Ltd.Inventor: Ryu Hirota