Patents by Inventor Ryu Hirota
Ryu Hirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7998847Abstract: Affords methods of manufacturing bulk III-nitride crystals whereby at least the surface dislocation density is low globally. The present III-nitride crystal manufacturing method includes: a step of preparing an undersubstrate (1) containing a III-nitride seed crystal, the III-nitride seed crystal having a matrix (1s), and inversion domains (1t) in which the polarity in the <0001> directions is inverted with respect to the matrix (1s); and a step of growing a III-nitride crystal (10) onto the matrix (1s) and inversion domains (1t) of the undersubstrate (1) by a liquid-phase technique; and is characterized in that a first region (10s), being where the growth rate of III-nitride crystal (10) growing onto the matrix (1s) is greater, covers second regions (10t), being where the growth rate of III-nitride crystal (10) growing onto the inversion domains (1t) is lesser.Type: GrantFiled: November 15, 2007Date of Patent: August 16, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Ryu Hirota, Koji Uematsu, Tomohiro Kawase
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Publication number: 20110065265Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.Type: ApplicationFiled: November 18, 2010Publication date: March 17, 2011Applicant: Sumitomo Electric Industries, Ltd.Inventors: Hitoshi KASAI, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Patent number: 7905958Abstract: A method of manufacturing group III-nitride semiconductor crystal includes the steps of accommodating an alloy containing at least a group III-metal element and an alkali metal element in a reactor, introducing a nitrogen-containing substance in the reactor, dissolving the nitrogen-containing substance in an alloy melt in which the alloy has been melted, and growing group III-nitride semiconductor crystal is provided. The group III-nitride semiconductor crystal attaining a small absorption coefficient and an efficient method of manufacturing the same, as well as a group III-nitride semiconductor device attaining high light emission intensity can thus be provided.Type: GrantFiled: March 30, 2005Date of Patent: March 15, 2011Assignees: Sumitomo Electric Industries, Ltd.Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Seiji Nakahata, Ryu Hirota
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Patent number: 7892513Abstract: Affords group III nitride crystal growth methods enabling crystal to be grown in bulk by a liquid-phase technique. One such method of growing group III nitride crystal from solution is provided with: a step of preparing a substrate having a principal face and including at least on its principal-face side a group III nitride seed crystal having the same chemical composition as the group III nitride crystal, and whose average density of threading dislocations along the principal face being 5×106 cm?2 or less; and a step of bringing into contact with the principal face of the substrate a solution in which a nitrogen-containing gas is dissolved into a group III metal-containing solvent, to grow group III nitride crystal onto the principal face.Type: GrantFiled: January 26, 2009Date of Patent: February 22, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shinsuke Fujiwara, Hiroaki Yoshida, Ryu Hirota, Koji Uematsu, Haruko Tanaka
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Patent number: 7858502Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.Type: GrantFiled: August 13, 2009Date of Patent: December 28, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hitoshi Kasai, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideyuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Publication number: 20100229786Abstract: A III-nitride crystal growth method that enables growing large-scale crystal under a liquid-phase technique is made available. The present III-nitride crystal growth method is a method of growing III-nitride crystal (10) by a liquid-phase technique, and is provided with: a step of preparing a III-nitride crystal substrate (1) having the same chemical composition as the III-nitride crystal (10), and having a thickness of not less than 0.5 mm; and a step of contacting onto a major surface (1m) of the III-nitride crystal substrate (1) a solution in which a nitrogen-containing gas (5) is dissolved in a solvent (3) that includes a Group-III metal, to grow III-nitride crystal (10) onto the major surface (1m).Type: ApplicationFiled: September 19, 2008Publication date: September 16, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Koji Uematsu, Hiroaki Yoshida, Ryu Hirota, Shinsuke Fujiwara, Haruko Tanaka
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Patent number: 7794543Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: February 13, 2008Date of Patent: September 14, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Patent number: 7771532Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.Type: GrantFiled: February 19, 2009Date of Patent: August 10, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
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Patent number: 7772585Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts , not burying the facets, maintaining the convex facet hills on ? and the network concavities on , excluding dislocations in the facet hills down to the outlining concavities on , forming a defect accumulating region H on , decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.Type: GrantFiled: June 6, 2006Date of Patent: August 10, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
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Publication number: 20100189624Abstract: Affords group III nitride crystal growth methods enabling crystal to be grown in bulk by a liquid-phase technique. One such method of growing group III nitride crystal from solution is provided with: a step of preparing a substrate having a principal face and including at least on its principal-face side a group III nitride seed crystal having the same chemical composition as the group III nitride crystal, and whose average density of threading dislocations along the principal face being 5×106 cm?2 or less; and a step of bringing into contact with the principal face of the substrate a solution in which a nitrogen-containing gas is dissolved into a group III metal-containing solvent, to grow group III nitride crystal onto the principal face.Type: ApplicationFiled: January 26, 2009Publication date: July 29, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Shinsuke Fujiwara, Hiroaki Yoshida, Ryu Hirota, Koji Uematsu, Haruko Tanaka
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Publication number: 20100090313Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.Type: ApplicationFiled: November 13, 2009Publication date: April 15, 2010Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Patent number: 7655960Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1?x?yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: GrantFiled: August 10, 2006Date of Patent: February 2, 2010Assignee: Sumito Electric Industries, Ltd.Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
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Publication number: 20100009526Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.Type: ApplicationFiled: August 13, 2009Publication date: January 14, 2010Applicant: Sumitomo Electric Industries, Ltd.Inventors: Hitoshi KASAI, Takuji OKAHISA, Shunsuke FUJITA, Naoki MATSUMOTO, Hideyuki IJIRI, Fumitaka SATO, Kensaku MOTOKI, Seiji NAKAHATA, Koji UEMATSU, Ryu HIROTA
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Publication number: 20090315150Abstract: Affords methods of manufacturing bulk III-nitride crystals whereby at least the surface dislocation density is low globally. The present III-nitride crystal manufacturing method includes: a step of preparing an undersubstrate (1) containing a III-nitride seed crystal, the III-nitride seed crystal having a matrix (1s), and inversion domains (1t) in which the polarity in the <0001> directions is inverted with respect to the matrix (1s); and a step of growing a III-nitride crystal (10) onto the matrix (1s) and inversion domains (1t) of the undersubstrate (1) by a liquid-phase technique; and is characterized in that a first region (10s), being where the growth rate of III-nitride crystal (10) growing onto the matrix (1s) is greater, covers second regions (10t), being where the growth rate of III-nitride crystal (10) growing onto the inversion domains (1t) is lesser.Type: ApplicationFiled: November 15, 2007Publication date: December 24, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Ryu Hirota, Koji Uematsu, Tomohiro Kawase
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Patent number: 7589000Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.Type: GrantFiled: December 22, 2006Date of Patent: September 15, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hitoshi Kasai, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideyuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Publication number: 20090215248Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1-x-yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: ApplicationFiled: April 28, 2009Publication date: August 27, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Seiji NAKAHATA, Ryu HIROTA, Kensaku MOTOKI, Takuji OKAHISA, Kouji UEMATSU
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Publication number: 20090155989Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts not burying the facets, maintaining the convex facet hills on ? and the network concavities on excluding dislocations in the facet hills down to the outlining concavities on forming a defect accumulating region H on decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.Type: ApplicationFiled: February 19, 2009Publication date: June 18, 2009Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Koji UEMATSU, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
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Patent number: 7534310Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: May 17, 2006Date of Patent: May 19, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Publication number: 20090071394Abstract: A low dislocation density AlxInyGa1-x-yN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing an AlxInyGa1-x-yN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: ApplicationFiled: November 18, 2008Publication date: March 19, 2009Applicant: SUMITOMO ELECTRONIC INDUSTRIES, LTD.Inventors: Seiji NAKAHATA, Ryu HIROTA, Kensaku MOTOKI, Takuji OKAHISA, Koji UEMATSU
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Publication number: 20090032907Abstract: It seems that a conventional method for producing a GaN crystal by using HVPE has a possibility that the crystallinity of a GaN crystal can be improved by producing a GaN crystal at a temperature higher than 1100° C. However, such a conventional method has a problem in that a quartz reaction tube (1) is melted when heated by heaters (5) and (6) to a temperature higher than 1100° C. Disclosed herein is a method for producing a GaxIn1-xN (0?x?1) crystal (12) by growing GaxIn1-xN (0?x?1) crystal (12) on the surface of a base substrate (7) by the reaction of a material gas, containing ammonia gas and at least one of a gallium halide gas and an indium halide gas, in a quartz reaction tube (1), wherein during the growth of GaxIn1-xN (0?x?1) crystal (12), quartz reaction tube (1) is externally heated and base substrate (7) is individually heated.Type: ApplicationFiled: August 17, 2006Publication date: February 5, 2009Inventors: Tomoki Uemura, Shinsuke Fujiwara, Takuji Okahisa, Ryu Hirota, Hideaki Nakahata