Patents by Inventor Ryu Hirota
Ryu Hirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7485484Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. The III-V crystals are obtained by manufacturing method characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2) in an atmosphere in which a patterning compound is present; and a step of growing a group III-V crystal (4) on the metal film after the heat treatment. Alternatively, the III-V crystal manufacturing method is characterized in including: a step of growing a group III-V compound buffer film on the metal film after the heat treatment; and a step of growing a group III-V crystal on the group III-V compound buffer film.Type: GrantFiled: October 12, 2007Date of Patent: February 3, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Patent number: 7473315Abstract: A low dislocation density AlxInyGa1-x-yN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing an AlxInyGa1-x-yN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: March 1, 2005Date of Patent: January 6, 2009Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Koji Uematsu
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Publication number: 20080299748Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. The III-V crystals are obtained by manufacturing method characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2) in an atmosphere in which a patterning compound is present; and a step of growing a group III-V crystal (4) on the metal film after the heat treatment. Alternatively, the III-V crystal manufacturing method is characterized in including: a step of growing a group III-V compound buffer film on the metal film after the heat treatment; and a step of growing a group III-V crystal on the group III-V compound buffer film.Type: ApplicationFiled: August 8, 2008Publication date: December 4, 2008Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Publication number: 20080283968Abstract: A method of manufacturing group III-nitride semiconductor crystal includes the steps of accommodating an alloy containing at least a group III-metal element and an alkali metal element in a reactor, introducing a nitrogen-containing substance in the reactor, dissolving the nitrogen-containing substance in an alloy melt in which the alloy has been melted, and growing group III-nitride semiconductor crystal is provided. The group III-nitride semiconductor crystal attaining a small absorption coefficient and an efficient method of manufacturing the same, as well as a group III-nitride semiconductor device attaining high light emission intensity can thus be provided.Type: ApplicationFiled: March 30, 2005Publication date: November 20, 2008Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Seiji Nakahata, Ryu Hirota
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Publication number: 20080202409Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: ApplicationFiled: February 13, 2008Publication date: August 28, 2008Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Patent number: 7354477Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: September 9, 2004Date of Patent: April 8, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Publication number: 20080038580Abstract: Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. The III-V crystals are obtained by manufacturing method characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2) in an atmosphere in which a patterning compound is present; and a step of growing a group III-V crystal (4) on the metal film after the heat treatment. Alternatively, the III-V crystal manufacturing method is characterized in including: a step of growing a group III-V compound buffer film on the metal film after the heat treatment; and a step of growing a group III-V crystal on the group III-V compound buffer film.Type: ApplicationFiled: October 12, 2007Publication date: February 14, 2008Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Publication number: 20080022921Abstract: A method of manufacturing a group III-nitride crystal substrate including the steps of introducing an alkali-metal-element-containing substance, a group III-element-containing substance and a nitrogen-element-containing substance into a reactor, forming a melt containing at least the alkali metal element, the group III-element and the nitrogen element in the reactor, and growing group III-nitride crystal from the melt, and characterized by handling the alkali-metal-element-containing substance in a drying container in which moisture concentration is controlled to at most 1.0 ppm at least in the step of introducing the alkali-metal-element-containing substance into the reactor is provided. A group III-nitride crystal substrate attaining a small absorption coefficient and the method of manufacturing the same, as well as a group III-nitride semiconductor device can thus be provided.Type: ApplicationFiled: April 15, 2005Publication date: January 31, 2008Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Seiji Nakahata, Ryu Hirota
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Publication number: 20080006201Abstract: The facet growth method grows GaN crystals by preparing an undersubstrate, forming a dotmask or a stripemask on the undersubstrate, growing GaN in vapor phase, causing GaN growth on exposed parts, suppressing GaN from growing on masks, inducing facets starting from edges of the masks and rising to tops of GaN crystals on exposed parts, maintaining the facets, making defect accumulating regions H on masked parts. attracting dislocations into the defect accumulating regions H on masks and reducing dislocation density of the surrounding GaN crystals on exposed parts. The defect accumulating regions H on masks have four types. The best of the defect accumulating regions H is an inversion region J. Occurrence of the inversion regions J requires preceding appearance of beaks with inversion orientation on the facets. Sufficient inversion regions J are produced at an initial stage by maintaining the temperature Tj at 900° C. to 990° C. without fail.Type: ApplicationFiled: July 18, 2007Publication date: January 10, 2008Inventors: Ryu Hirota, Kensaku Motoki, Seiji Nakahata, Takuji Okahisa, Koji Uematsu
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Publication number: 20070296061Abstract: A method of manufacturing a group III-nitride crystal substrate including the steps of introducing an alkali-metal-element-containing substance, a group III-element-containing substance and a nitrogen-element-containing substance into a reactor, forming a melt containing at least the alkali metal element, the group III-element and the nitrogen element in the reactor, and growing group III-nitride crystal from the melt, and characterized by handling the alkali-metal-element-containing substance in a drying container in which moisture concentration is controlled to at most 1.0 ppm at least in the step of introducing the alkali-metal-element-containing substance into the reactor is provided. A group III-nitride crystal substrate attaining a small absorption coefficient and the method of manufacturing the same, as well as a group III-nitride semiconductor device can thus be provided.Type: ApplicationFiled: March 30, 2005Publication date: December 27, 2007Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Ryu Hirota, Seiji Nakahata
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Publication number: 20070280872Abstract: The GaN facet growth method produces defect accumulating regions H on masks by forming a dotmask or a stripemask on an undersubstrate, growing GaN in a reaction furnace in vapor phase, inducing GaN crystals on exposed parts without covering the masks, inviting facets starting from verges of the masks and producing defect accumulating regions H on the mask. The defect accumulating regions H have four versions, that is, non (O), polycrystal (P), c-axis inclining single crystal (A) and orientation inversion (J). The best is the orientation inversion region (J). A sign of occurrence of the orientation inversion regions (J) is beaks of inversion orientation appearing on facets. GaN is grown on a masked undersubstrate by supplying a carbon material at a hydrocarbon partial pressure of 10 Pa to 5 kPa for 0.5 hour to 2 hour by an HVPE facet growth method without burying facets.Type: ApplicationFiled: June 5, 2007Publication date: December 6, 2007Inventors: Takuji Okahisa, Kensaku Motoki, Koji Uematsu, Seiji Nakahata, Ryu Hirota, Hideyuki Ijiri, Hitoshi Kasai, Shunsuke Fujita, Fumitaka Sato, Toru Matsuoka
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Patent number: 7303630Abstract: Dotted seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations from neighboring regions, accumulate the dislocations into pit bottoms, and make closed defect accumulating regions (H) on the seeds. The polycrystalline or slanting orientation single crystal closed defect accumulating regions (H) induce microcracks due to thermal expansion anisotropy. The best one is orientation-inversion single crystal closed defect accumulating regions (H). At an early stage, orientation-inverse protrusions are induced on tall facets and unified with each other above the seeds. Orientation-inverse crystals growing on the unified protrusions become the orientation-inverse single crystal closed defect accumulating regions (H).Type: GrantFiled: September 3, 2004Date of Patent: December 4, 2007Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Takuji Okahisa, Ryu Hirota, Seiji Nakahata, Koji Uematsu
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Patent number: 7297625Abstract: A method of manufacturing a group III-V crystal is made available by which good-quality group III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates. A method of manufacturing a group III-V crystal, characterized in including: a step of depositing a metal film (2) on a substrate (1); a step of heat-treating the metal film (2) in an atmosphere in which a patterning compound is present; and a step of growing a group III-V crystal (4) on the metal film after the heat treatment. Additionally, a method of manufacturing a group III-V crystal, characterized in including: a step of growing a group III-V compound buffer film on the metal film after the heat treatment; and a step of growing a group III-V crystal on the group III-V compound buffer film.Type: GrantFiled: April 1, 2004Date of Patent: November 20, 2007Assignee: Sumitomo Electric Industries, Ltd.Inventors: Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Patent number: 7288151Abstract: There is provided a method of manufacturing a group-III nitride crystal in which a nitrogen plasma is brought into contact with a melt containing a group-III element and an alkali metal to grow the group-III nitride crystal. Furthermore, there is also provided a method of manufacturing a group-III nitride crystal in which the group-III nitride crystal is grown on a substrate placed in a melt containing a group-III element and an alkali metal, with a minimal distance between a surface of the melt and a surface of the substrate set to be at most 50 mm.Type: GrantFiled: November 29, 2004Date of Patent: October 30, 2007Assignees: Sumitomo Electric Industries, Ltd.Inventors: Takatomo Sasaki, Yusuke Mori, Masashi Yoshimura, Fumio Kawamura, Ryu Hirota
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Publication number: 20070148920Abstract: A fabrication method of a group III nitride crystal substance includes the steps of cleaning the interior of a reaction chamber by introducing HCl gas into the reaction chamber, and vapor deposition of a group III nitride crystal substance in the cleaned reaction chamber. A fabrication apparatus of a group III nitride crystal substance includes a configuration to introduce HCl gas into the reaction chamber, and a configuration to grow a group III nitride crystal substance by HVPE. Thus, a fabrication method of a group III nitride crystal substance including the method of effectively cleaning deposits adhering inside the reaction chamber during crystal growth, and a fabrication apparatus employed in the fabrication method are provided.Type: ApplicationFiled: December 22, 2006Publication date: June 28, 2007Inventors: Hitoshi Kasai, Takuji Okahisa, Shunsuke Fujita, Naoki Matsumoto, Hideyuki Ijiri, Fumitaka Sato, Kensaku Motoki, Seiji Nakahata, Koji Uematsu, Ryu Hirota
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Publication number: 20060273343Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. An AlxInyGa1?x?yN (0?x?1, 0?y?1, 0<x+y?1) mixture crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: ApplicationFiled: August 10, 2006Publication date: December 7, 2006Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Seiji Nakahata, Ryu Hirota, Kensaku Motoki, Takuji Okahisa, Kouji Uematsu
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Publication number: 20060272572Abstract: A nitride semiconductor crystal substrate is produced by forming a network mask repeating a closed loop unit shape upon an undersubstrate, growing a nitride semiconductor crystal in vapor phase, producing convex facet hills covered with facets on exposed parts ?, forming outlining concavities on mask-covered parts ?, not burying the facets, maintaining the convex facet hills on ? and the network concavities on ?, excluding dislocations in the facet hills down to the outlining concavities on ?, forming a defect accumulating region H on ?, decreasing dislocations in the facet hills and improving the facet hills to low defect density single crystal regions Z, producing a rugged nitride crystal, and slicing and polishing the nitride crystal into mirror nitride crystal wafers. After the fabrication of devices on the nitride wafer, dry-etching or wet etching of hot KOH or NaOH divides the device-carrying wafer into chips by corroding the network defect accumulating region H.Type: ApplicationFiled: June 6, 2006Publication date: December 7, 2006Inventors: Koji Uematsu, Fumitaka Sato, Ryu Hirota, Seiji Nakahata, Hideaki Nakahata
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Patent number: 7129525Abstract: Affords semiconductor light-emitting devices in which generation of spontaneous electric fields in the active layer is reduced to enable enhanced brightness. Semiconductor light-emitting device (1) is furnished with an n-type cladding layer (3), a p-type cladding layer (7) provided over the n-type cladding layer (3), and an active layer (5) composed of a nitride and provided in between the n-type cladding layer (3) and the p-type cladding layer (7), and therein is characterized in that the angle formed by an axis orthogonal to the interface between the n-type cladding layer (3) and the active layer (5), and the c-axis in the active layer (5), and the angle formed by an axis orthogonal to the interface between the active layer (5) and the p-type cladding layer (7), and the c-axis in the active layer (5), are each greater than zero.Type: GrantFiled: April 28, 2005Date of Patent: October 31, 2006Assignee: Sumitomo Electric Industries, Ltd.Inventors: Koji Uematsu, Masaki Ueno, Ryu Hirota, Hideaki Nakahata, Manabu Okui
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Publication number: 20060213429Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: ApplicationFiled: May 17, 2006Publication date: September 28, 2006Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Patent number: 7112826Abstract: Seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations to the pit bottoms from neighboring regions and make closed defect accumulating regions (H) under the facet bottoms. The closed defect accumulating regions (H) arrest dislocations permanently. Release of dislocations, radial planar defect assemblies and linear defect assemblies are forbidden. The surrounding accompanying low dislocation single crystal regions (Z) and extra low dislocation single crystal regions (Y) are low dislocation density single crystals.Type: GrantFiled: November 5, 2003Date of Patent: September 26, 2006Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Takuji Okahisa, Seiji Nakahata, Ryu Hirota, Koji Uematsu