Abstract: A semiconductor module having heat sink plates and an insulating plate laminated under the semiconductor chips, wherein the thickness of the support base plate is set to be 2.5 times in thickness of the insulating plate, which is the maximum thickness among the heat sink plates and the insulating plate laminated in the semiconductor module, so that the thermal fatigue lives of the solder layers are balanced, and the life of the whole semiconductor module can be prolonged.

Abstract: A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

Abstract: A semiconductor integrated circuit device capable of having a high integration density and excellent performance and a method of fabricating the semiconductor integrated circuit device are disclosed. In this semiconductor integrated circuit device, a connecting conductor for connecting gate wiring which is formed on a field oxide film and extended from the gate of a MOSFET, to the source/drain region of another MOSFET is interposed between the gate wiring and one of two side space layers for defining the width of the gate wiring.

Abstract: Disclosed is a semiconductor device having a support region, an element-forming region (e.g., an epitaxial layer) and a buried layer between the support region and the element-forming region, with at least one of a MOS element and a bipolar element being formed in the element-forming region. The feature of the present invention resides in that atoms of at least one element selected from oxygen, nitrogen, carbon, argon, neon, krypton and helium is contained in a layer in at least one of the element-forming region and the buried layer, so as to suppress auto-doping of impurities from the buried layer into the element-forming region and suppress swelling of the buried layer.

Abstract: A semiconductor memory including two cross-coupled driver MOS transistors respectively having source and drain regions within a semiconductor substrate and each of the drain regions being in ohmic contact with the gate electrode of the other driver MOS transistor. The gate electrodes of the driver MOS transistors are formed in a first-level polycrystalline silicon (polysilicon) layer and the two transfer MOS transistors respectively have their source and drain regions formed in portions of a second-level polysilicon layer. The driver regions are formed so as to be independently brought into ohmic contact with the respective drain regions of the driver MOS transistors, and each of the transfer MOS transistors have a gate electrode effected in a third-level polysilicon layer which also defines a word line.

Abstract: A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the well from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.

Abstract: The present invention relates to a semiconductor device including a MOS transistor which is formed with a source region, a drain region and a channel region by the use of polycrystalline silicon, and a method of manufacturing the semiconductor device. Ions of carbon, oxygen or/and nitrogen are introduced into a polycrystalline silicon layer over the whole area thereof, and restrain conductive ions in the source and drain regions from diffusing into the channel region.

Abstract: A monolithic complementary semiconductor device comprising n-type and p-type well regions separated by a dielectric isolation region extending from the surface into the substrate region. The well region includes a highly doped buried region which is located at the bottom of the well region and separates an active region in the wall from the substrate region. The isolation region is deeper than the buried region. The well-to-well isolation is enhanced by the combination of the buried region and the deep dielectric isolation region. Packing density and the high speed operation can also be improved.