Patents by Inventor Saeng-Hwan Kim

Saeng-Hwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490255
    Abstract: Provided is a periodic signal generation circuit including: a clock generation unit suitable for generating first to Nth clocks which have a basic period and have a phase increasing sequentially by a time interval obtained by dividing the basic period by “N”; a pulse generation unit suitable for generating first to Nth periodic pulses having an equal pulse width and having a phase increasing sequentially by a time interval obtained by dividing the basic period by “N” by combining two or more clocks among the first to Nth clocks; and a periodic signal generation unit suitable for generating a periodic signal by combining one or more periodic pulses among the first to Nth periodic pulses depending on combination information.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: November 26, 2019
    Assignee: SK hynix Inc.
    Inventors: Seung-Chan Kim, Saeng-Hwan Kim, Sang-Hoon Lee
  • Patent number: 10379786
    Abstract: A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: August 13, 2019
    Assignee: SK hynix Inc.
    Inventors: Mun Seon Jang, Saeng Hwan Kim, Chang Ki Baek, Jae Woong Yun
  • Patent number: 10249359
    Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: April 2, 2019
    Assignee: SK hynix Inc.
    Inventors: Chul-Moon Jung, Saeng-Hwan Kim
  • Patent number: 10234888
    Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: March 19, 2019
    Assignee: SK hynix Inc.
    Inventors: Kyeong-Tae Kim, Chang-Hyun Lee, Jae-Boum Park, Saeng-Hwan Kim
  • Publication number: 20180259992
    Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.
    Type: Application
    Filed: May 11, 2018
    Publication date: September 13, 2018
    Inventors: Kyeong-Tae KIM, Chang-Hyun LEE, Jae-Boum PARK, Saeng-Hwan KIM
  • Publication number: 20180259993
    Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.
    Type: Application
    Filed: May 11, 2018
    Publication date: September 13, 2018
    Inventors: Kyeong-Tae KIM, Chang-Hyun LEE, Jae-Boum PARK, Saeng-Hwan KIM
  • Patent number: 10024915
    Abstract: A semiconductor device may include an inversion control signal generation circuit, a pattern control signal generation circuit, and a data input/output (I/O) circuit. The inversion control signal generation circuit may generate an inversion control signal according to a logic level combination of bit patterns included in at least one of a first address and a second address. The pattern control signal generation circuit may generate a pattern control signal from a pre-control signal in response to the inversion control signal. In response to the pattern control signal, the data input/output (I/O) circuit may generate data signals that will be output to an internal I/O line based on data signals loaded on a local I/O line.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: July 17, 2018
    Assignee: SK hynix Inc.
    Inventors: Dong Hee Han, Saeng Hwan Kim, In Tae Kim, Byoung Chul Lee, Mun Seon Jang
  • Patent number: 10014073
    Abstract: A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: July 3, 2018
    Assignee: SK hynix Inc.
    Inventors: Mun Seon Jang, Saeng Hwan Kim, In Tae Kim, Chang Ki Baek
  • Patent number: 9996098
    Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 12, 2018
    Assignee: SK Hynix Inc.
    Inventors: Kyeong-Tae Kim, Chang-Hyun Lee, Jae-Boum Park, Saeng-Hwan Kim
  • Publication number: 20180151216
    Abstract: Provided is a periodic signal generation circuit including a clock generation unit suitable for generating first to Nth clocks which have a basic period and have a phase increasing sequentially by a time interval obtained by dividing the basic period by “N”; a pulse generation unit suitable for generating first to Nth periodic pulses having an equal pulse width and having a phase increasing sequentially by a time interval obtained by dividing the basic period by “N” by combining two or more clocks among the first to Nth clocks; and a periodic signal generation unit suitable for generating a periodic signal by combining one or more periodic pulses among the first to Nth periodic pulses depending on combination information.
    Type: Application
    Filed: January 24, 2018
    Publication date: May 31, 2018
    Inventors: Seung-Chan KIM, Saeng-Hwan KIM, Sang-Hoon LEE
  • Patent number: 9916886
    Abstract: Provided is a periodic signal generation circuit including: a clock generation unit suitable for generating first to Nth clocks which have a basic period and have a phase increasing sequentially by a time interval obtained by dividing the basic period by “N”; a pulse generation unit suitable for generating first to Nth periodic pulses having an equal pulse width and having a phase increasing sequentially by a time interval obtained by dividing the basic period by “N” by combining two or more clocks among the first to Nth clocks; and a periodic signal generation unit suitable for generating a periodic signal by combining one or more periodic pulses among the first to Nth periodic pulses depending on combination information.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: March 13, 2018
    Assignee: SK Hynix Inc.
    Inventors: Seung-Chan Kim, Saeng-Hwan Kim, Sang-Hoon Lee
  • Publication number: 20170372796
    Abstract: A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.
    Type: Application
    Filed: December 7, 2016
    Publication date: December 28, 2017
    Inventors: Mun Seon JANG, Saeng Hwan KIM, In Tae KIM, Chang Ki BAEK
  • Publication number: 20170337105
    Abstract: A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.
    Type: Application
    Filed: September 7, 2016
    Publication date: November 23, 2017
    Inventors: Mun Seon JANG, Saeng Hwan KIM, Chang Ki BAEK, Jae Woong YUN
  • Publication number: 20170336471
    Abstract: A semiconductor device may include an inversion control signal generation circuit, a pattern control signal generation circuit, and a data input/output (I/O) circuit. The inversion control signal generation circuit may generate an inversion control signal according to a logic level combination of bit patterns included in at least one of a first address and a second address. The pattern control signal generation circuit may generate a pattern control signal from a pre-control signal in response to the inversion control signal. In response to the pattern control signal, the data input/output (I/O) circuit may generate data signals that will be output to an internal I/O line based on data signals loaded on a local I/O line.
    Type: Application
    Filed: September 16, 2016
    Publication date: November 23, 2017
    Inventors: Dong Hee HAN, Saeng Hwan KIM, In Tae KIM, Byoung Chul LEE, Mun Seon JANG
  • Publication number: 20170242754
    Abstract: Semiconductor device including an input and output line control circuit may be provided. The input/output line control circuit may include a write connection circuit configured to transmit data of a write local line pair based on a write control signal. The input/output line control circuit may include a connection circuit configured to transmit data received from the write connection circuit to a write segment line pair based on a switching signal. The input/output line control circuit may be configured to transmit data of the write local line pair to the write segment line pair, based on the switching signal and the write control signal.
    Type: Application
    Filed: June 1, 2016
    Publication date: August 24, 2017
    Inventors: Mun Seon JANG, Saeng Hwan KIM, Bo Yeun KIM
  • Publication number: 20170235324
    Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.
    Type: Application
    Filed: June 30, 2016
    Publication date: August 17, 2017
    Inventors: Kyeong-Tae KIM, Chang-Hyun LEE, Jae-Boum PARK, Saeng-Hwan KIM
  • Patent number: 9711193
    Abstract: A driving signal control circuit includes a discharge circuit, a counter circuit, and a control circuit. The discharge circuit is configured to compare a monitored voltage and a reference voltage, and generate a discharge signal. The monitored voltage is proportional to a core voltage. The counter circuit is configured to perform an up/down count operation according to the discharge signal, and generate a count signal. The control circuit is configured to generate a driving signal which has an enable period proportional to the count signal.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: July 18, 2017
    Assignee: SK hynix Inc.
    Inventors: Man Keun Kang, Saeng Hwan Kim
  • Publication number: 20170194043
    Abstract: Provided is a periodic signal generation circuit including: a clock generation unit suitable for generating first to Nth clocks which have a basic period and have a phase increasing sequentially by a time interval obtained by dividing the basic period by “N”; a pulse generation unit suitable for generating first to Nth periodic pulses having an equal pulse width and having a phase increasing sequentially by a time interval obtained by dividing the basic period by “N” by combining two or more clocks among the first to Nth clocks; and a periodic signal generation unit suitable for generating a periodic signal by combining one or more periodic pulses among the first to Nth periodic pulses depending on combination information.
    Type: Application
    Filed: June 8, 2016
    Publication date: July 6, 2017
    Inventors: Seung-Chan KIM, Saeng-Hwan KIM, Sang-Hoon LEE
  • Publication number: 20170186476
    Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.
    Type: Application
    Filed: March 15, 2017
    Publication date: June 29, 2017
    Inventors: Chul-Moon JUNG, Saeng-Hwan KIM
  • Patent number: 9673814
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals. The second semiconductor device may generate a start signal in response to the set signals, generate an input control code and an output control code from the set signals in response to the start signal, generate a frequency determination signal including information on an operation frequency in response to the output control code, and control an internal operation in response to the frequency determination signal.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: June 6, 2017
    Assignee: SK hynix Inc.
    Inventors: Won Kyung Chung, Saeng Hwan Kim