Abstract: The present invention discloses a delay circuit having a constant delay time. The delay circuit comprises an electric wire for transmitting a driving signal from a driver; a capacitor connected between said electric wire and ground, and for delaying transmission of said driving signal; and a current source connected to said electric wire and capacitor in parallel, and for keeping an amount of an electric current applied to said capacitor constant when a signal applied to said capacitor is varied.

Abstract: A data register circuit, comprising: input means which includes a first input portion and a second input portion, the first input portion being reset by a data reset signal and buffering a data signal from a data line in accordance with a data fetch signal and the second input portion being reset by a data reset signal and buffering a data bar signal from a data bar line in accordance with the data fetch signal; storing means which includes a first flip flop and a second flip flop, the first and second flip flops for respectively receiving output signals of the first and second input portions of the input means and providing inverting signals of the output signals of the first and second input portions until the output signals of the first and second input portions are changed by the data reset signal, a first latch which is connected between the first input portion and the first flip flop and temporarily stores the output signal of the first input portion and a second latch which is connected between the sec

Abstract: The present invention discloses a method and a device for automatically performing a refresh operation, which can reduce power consumption in an auto refresh mode of a semiconductor memory device. The power consumption can be reduced by controlling the operation of input buffers or the operation of an input buffer generator for controlling the input buffers, during the auto refresh operation.

Abstract: A multi-driving apparatus by a multi-level detection which pluralizes a voltage detection level in order to effectively operate voltage generators in the voltage generation circuit, minimizes a level fluctuation, reduces noise influenced on a total operation of the apparatus, increases a reliability of the apparatus, and reduces the power-consumption.

Abstract: The voltage control generator for a semiconductor device is disclosed, in which the substrate bias voltage through the oscillation period of the step-up voltage generator circuit are quickly adjusted with respect to the level variation of a corresponding voltage. The circuit according to the present invention includes a control level generator generating at least one control signal for detecting a substrate bias voltage level from a substrate of a semiconductor device and adjusting the width of an oscillation period to a set level in accordance with the detected signal, a voltage control oscillator generating a signal in which the width of an oscillation period is varied to the set level in response to an output signal from the control level generator, and a charge pump supplying a stable bias voltage to the substrate of the semiconductor device by increasing or decreasing a pumping speed in response to an output signal from the voltage control oscillator.