Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals. The second semiconductor device may generate a start signal in response to the set signals, generate an input control code and an output control code from the set signals in response to the start signal, generate a frequency determination signal including information on an operation frequency in response to the output control code, and control an internal operation in response to the frequency determination signal.

Abstract: A sense amplifier driving device, and more particularly, a technology for improving the post overdriving operation characteristic of a semiconductor device. A sense amplifier driving device includes a driving signal generation block configured to compare a reference voltage set by a voltage trimming signal and a level of a power supply voltage, and generate a pull-up driving signal for controlling an operation of a sense amplifier; and a sense amplifier driving block configured to supply a driving voltage to a pull-up power line of the sense amplifier for an active operation period in correspondence to the pull-up driving signal, the driving signal generation block including a voltage divider configured to divide the power supply voltage, and output a divided voltage; and a voltage comparison section configured to compare the reference voltage and the divided voltage, and output a control signal for controlling an overdriving operation of the sense amplifier.

Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output set signals. The second semiconductor device may generate a start signal in response to the set signals, generate an input control code and an output control code from the set signals in response to the start signal, generate a frequency determination signal including information on an operation frequency in response to the output control code, and control an internal operation in response to the frequency determination signal.

Abstract: A driving signal control circuit includes a discharge circuit, a counter circuit, and a control circuit. The discharge circuit is configured to compare a monitored voltage and a reference voltage, and generate a discharge signal. The monitored voltage is proportional to a core voltage. The counter circuit is configured to perform an up/down count operation according to the discharge signal, and generate a count signal. The control circuit is configured to generate a driving signal which has an enable period proportional to the count signal.

Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.

Abstract: A sense amplifier driving device, and more particularly, a technology for improving the post overdriving operation characteristic of a semiconductor device. A sense amplifier driving device includes a driving signal generation block configured to compare a reference voltage set by a voltage trimming signal and a level of a power supply voltage, and generate a pull-up driving signal for controlling an operation of a sense amplifier; and a sense amplifier driving block configured to supply a driving voltage to a pull-up power line of the sense amplifier for an active operation period in correspondence to the pull-up driving signal, the driving signal generation block including a voltage divider configured to divide the power supply voltage, and output a divided voltage; and a voltage comparison section configured to compare the reference voltage and the divided voltage, and output a control signal for controlling an overdriving operation of the sense amplifier.

Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.

Abstract: A semiconductor device may include a first channel provided in a first die. The semiconductor device may include a second channel provided in a second die and disposed adjacent to the first channel, and configured to exchange signals and data with the first channel. The first channel and the second channel may receive and output calibration-related signals from and to each other through bonding, and may share calibration start signals. The calibration start signal may be respectively generated in the first channel and the second channel.

Abstract: An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

Abstract: A memory may include a plurality of word lines, one or more redundancy word lines for replacing one or more word lines among the plurality of word lines, a target address generation unit suitable for generating one or more target addresses using a stored address, and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, refreshing a word line selected based on the target address when the refresh command is inputted M times, and refreshing the one or more redundancy word lines whenever the refresh command is inputted N times, wherein the M and N are natural numbers.

Abstract: A temperature sensor includes: a gate voltage generation unit including a bias resistor, a first source resistor, and a first MOS transistor and configured to generate a gate voltage; and a variable voltage output unit including an output resistor, a second source resistor, and a second MOS transistor and configured to generate the variable voltage.

Abstract: A memory may include a plurality of word lines, one or more redundancy word lines for replacing one or more word lines among the plurality of word lines, a target address generation unit suitable for generating one or more target addresses using a stored address, and a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is periodically inputted, refreshing a word line selected based on the target address when the refresh command is inputted M times, and refreshing the one or more redundancy word lines whenever the refresh command is inputted N times, wherein the M and N are natural numbers.

Abstract: A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip.

Abstract: A internal voltage generator includes a plurality of voltage level detection units, each configured to detect a voltage level of a corresponding internal voltage terminal, based on a predetermined target voltage level assigned to the corresponding internal voltage terminal, and generate a detection signal, a common internal voltage generation unit configured to generate an internal voltage through a pumping operation in response to the detection signal outputted from the voltage level detection units, and a path multiplexing unit configured to selectively output the internal voltage to one of the internal voltage terminals.

Abstract: A temperature sensor includes a counting signal generation unit, a counting signal decoding unit, an input reference voltage selection unit, and a latch pulse generation unit. The counting signal generation unit is configured to generate one or more counting signals in response to an oscillation signal. The counting signal decoding unit is configured to decode the one or more counting signals and to generate one or more test selection signals and an end signal. The input reference voltage selection unit is configured to output a first selection reference voltage or a second selection reference voltage as an input reference voltage in response to the one or more test selection signals. The latch pulse generation unit is configured to generate one or more latch pulses in response to the one or more test selection signals.

Abstract: A semiconductor memory device includes: a repair address generation unit configured to generate a repair address signal in response to a first address signal; a line choice address generation unit configured to generate a line choice address signal by combining the first address signal and the repair address signal according to a determination as to whether the repair address signal is to be used; and a cell line decoding unit configured to select one of a normal cell region and a redundancy cell region according to the determination, and select one of a plurality of local cell lines provided in the selected cell region in response to the line choice address signal.

Abstract: A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip.

Abstract: A temperature sensor includes: a gate voltage generation unit including a bias resistor, a first source resistor, and a first MOS transistor and configured to generate a gate voltage; and a variable voltage output unit including an output resistor, a second source resistor, and a second MOS transistor and configured to generate the variable voltage.