Abstract: The present invention provides a method of forming a vertical replacement gate (VRG) device on a semiconductor substrate. The method includes depositing an epitaxial layer over a first source/drain region, implanting a layer within the epitaxial layer wherein the thickness of the layer substantially defines a channel length of the device and replacing the layer with a gate layer.

Abstract: The present invention provides a die located on a semiconductor wafer. In one embodiment, the die includes a circuit region located within a circuit perimeter of the die. In addition, the die includes a bond pad region located between the circuit perimeter and an outer perimeter of the die. Also the die includes an alignment mark located within the bond pad region.

Abstract: A Method and computer implemented system may be used to value knowledge-based property such as documents, databases, spreadsheets or research and development related information or studies. Intangible property may be valued by analyzing stored data representing accesses by users to a medium containing a copy of the knowledge-based property, estimating a pattern of the accesses by users to the medium containing the copy of the knowledge-based property using a statistical model, and assigning a value to the knowledge-based property based on the pattern. The data may comprise the total number of times the copy of the knowledge-based property has been accessed and a time-date stamp for each access event. The assigned values for a plurality of knowledge-based properties may then be used as bases for making decisions such as apportioning budget resources among tasks or projects related to the knowledge-based properties or apportioning availability of limited computer resources for storing shared documents.

Abstract: An architecture and process for forming CMOS vertical replacement gate metal oxide semiconductor field-effect transistors is disclosed. The integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second source/drain dopes regions formed in the surface. An insulating trench is formed between the first and second source/drain regions. A third doped region forming a channel of a different conductivity type than the first source/drain region is positioned over the first source/drain region. A fourth doped region is formed over the second source/drain region, having an opposite conductivity type with respect to the second source/drain region, and forming a channel region. Fifth and sixth source/drain regions are formed respectively over the third and fourth doped regions.

Abstract: An integrated circuit that includes I/O circuitry that may or may not be protected from ESD damage. The protection from ESD damage may be selectively deactivated or activated or may not be present at all in one or more of the I/O circuits. In use, the integrated circuit may be coupled to another integrated circuit to form a multi-chip module where the ESD protection for the I/O circuitry between the modules is deactivated or not present. This is advantageous because the likelihood of ESD damage to this I/O circuitry is reduced once the multi-chip module is formed. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.

Abstract: A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.

Abstract: A semiconductor device comprising a silicon-on-insulator (SOI) substrate including a base substrate, an insulator layer, and a silicon layer, and a trench capacitor including at least one trench formed in the silicon-on-insulator substrate and extending through the base substrate, the insulator layer and the silicon layer, wherein the at least one trench includes at least one layer of silicon dioxide formed therein. In a preferred embodiment, semiconductor material disposed in the at least one trench forms a first electrode of a semiconductor capacitor, and semiconductor material of the SOI substrate which lies adjacent to the at least one trench forms a second electrode of the capacitor.

Abstract: The present invention provides a method of forming a trench capacitor in an input/output region and a trench isolation structure in an active device region and a method of manufacturing an integrated circuit using the aforementioned method of forming. The invention comprises concurrently forming an isolation trench in an active region and a capacitive trench in an input/output region, concurrently forming a dielectric layer over the walls of the isolation trench and the capacitive trench, and forming a conductive material in the capacitive trench.

Abstract: A method for forming shallow trench isolation structures produces a shallow trench isolation structure having a substantially planar upper surface. The shallow trench isolation structure is formed from an originally formed shallow trench isolation structure which includes a deposited dielectric material within a trench and which exhibits dishing related problems in the form of a void formed within the trench, wherein the surface of the deposited dielectric material is recessed below the planar upper surface. The method provides for filling the void with a silicon film. The silicon film is then polished in its as-deposited or oxidized form, to produce a shallow trench isolation structure having a planar upper surface.

Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.

Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.

Abstract: An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent diffusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer.

Abstract: The specification describes techniques for wire bonding gold wires to copper metallization in semiconductor integrated circuits. A barrier layer is formed on the copper, and an aluminum bonding pad is formed on the barrier layer. Gold wire is then thermocompression bonded to the aluminum pad.

Abstract: The invention includes a process for copper metallization of an integrated circuit, comprising the steps of forming tantalum on a substrate, forming tantalum nitride over the tantalum, forming titanium nitride over the tantalum nitride, forming copper over the titanium nitride and integrated circuits made thereby. The invention is particularly useful in forming damascene structures with large aspect ratios.

Abstract: A process for forming isolated active device regions on a silicon substrate comprises the steps of forming at least one trench in a silicon substrate to define at least two active device regions on the substrate to be isolated from each other, depositing an electrically insulative material on the substrate to fill the trench with the material, planarizing the surface of the substrate, performing a masking and etching operation to expose at least one active device region on the substrate, selectively growing a first epitaxial layer of silicon on the exposed active device region, masking the substrate to leave exposed at least one other active device region on the substrate, selectively growing a second epitaxial layer of silicon on the other exposed active device region, the first epitaxial layer and second epitaxial layer being doped with dopant atoms to the same or different dopant concentration to provide, at least two isolated active device regions on the silicon substrate.

Abstract: The present invention provides a method of forming a vertical replacement gate (VRG) device on a semiconductor substrate. The method includes depositing an epitaxial layer over a first source/drain region, implanting a layer within the epitaxial layer wherein the thickness of the layer substantially defines a channel length of the device and replacing the layer with a gate layer.

Abstract: The invention includes a method for manufacturing a merged contact in a window, comprising opening a window to one of a source and a drain of a field effect transistor and to and only partially overlapping a gate electrode of the field effect transistor, and depositing an electrical conductor connecting the gate electrode with one of the source and the drain to provide a merged contact between the gate and one of the source and the drain. Also described are devices made thereby.

Abstract: A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.

Abstract: A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.

Abstract: A trench capacitor formed on an SOI substrate extends through an upper silicon layer and an insulating layer and into a semiconductor base substrate. The outer electrode of the trench capacitor includes portions of the semiconductor base substrate which bound the trench in which the trench capacitor is formed. The outer electrode is coupled to a contact structure formed in close proximity to the trench capacitor, and which extends through the insulating layer. The method for simultaneously producing the trench capacitor and contact structure includes forming two trench openings, forming a dielectric liner on one of the trench openings, then filling each of the trench openings with a semiconductor material.