Abstract: A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an antireflective coating to prevent rainbowing or spiking of the coating into the underlying metal.

Abstract: In a method of incorporating BIST (built-in self test) circuitry in an integrated circuit, at least one metal layer is arranged to relieve stress in the substrate under bond pads from wire attachment to these pads. By providing at least one stress relieving metal layer, which can be incorporated into electrical paths of the bond pads and related circuitry, BIST circuitry can be provided, at least partly, in the conventionally non-active semiconductive portion of the substrate under the bond pad. The method allows BIST circuitry to occupy conventionally non-active areas under the bond pads wherein leakage current from stress cracks in dielectric layers under the bond pads can be redirected to a metal layer.

Abstract: A bond pad support structure is located beneath a bond pad on an integrated circuit. The bond pad support structure includes a first bond pad support layer at least partly located below the bond pad. The first bond pad support layer has a plurality of radial patterns with at least one space between the radial patterns. The radial patterns may be, for example, straight lines having approximately uniform thickness. Alternatively, the radial patterns may be triangles, each of which has an apex pointing to the center of a region below the bond pad. The radial patterns may have a plurality of different lengths. A second bond pad support layer is located on the first bond pad support layer. The second bond pad support layer fills at least a portion of the space between the radial patterns.

Abstract: A process for fabricating novel dual-polysilicon structures comprises forming trenches of differing depths in a field oxide that overlies a substrate. Utilizing an ion implantation barrier in the trenches, ion implantation is performed to create self-aligned structures. Importantly, polysilicon is formed in the trenches in a single deposition.

Abstract: Microwave radiation, perhaps with microwave absorbing materials, is utilized to provide heating of partially formed integrated circuits in a variety of circumstances.

Abstract: A twin tub integrated circuit and method for its formation are disclosed. A portion of the substrate is covered by photoresist while an n region is formed, illustratively, by ion implantation. Then the n region is covered with a protective material, illustratively a spin on glass or another photoresist. The previously-formed photoresist is removed and a p-type implant is performed to create an p region. When all the protective layers are removed, both regions have upper surfaces which are co-planar. The co-planar surfaces, a departure from previous practice, make submicron lithography easier. The regions are annealed to form twin tubs.

Abstract: The present invention provides a bond pad support structure for use in an integrated circuit having a bond pad located thereon. In one embodiment, the bond pad support structure comprises a support layer that is located below the bond pad and that has an opening formed therein. The bond pad support structure further includes a dielectric layer that is located on the conductive layer and that extends at least partially into the opening to form a bond pad support surface over at least a portion of the opening. The first bond pad support layer, in one embodiment, may comprise a conductive metal and the second bond pad support layer may comprise of a dielectric material. The present invention provides a unique bond pad structure wherein an opening within a first bond pad support layer is at least partially filled with a second bond pad support layer.

Abstract: The specification describes a composite TiN barrier layer structure formed by depositing a first TiN layer by CVD to obtain good step coverage, followed by a second TiN layer formed by PVD to obtain uniform surface morphology for subsequent deposition of an aluminum alloy contact layer. Alternatively, uniform TiN layer morphology is obtained by depositing multiple CVD TiN layers as a series of thin strata, and passivating after each deposition step to fully crystallize each stratum thereby obtaining a uniformly crystallized barrier layer.

Abstract: The present invention provides, in one embodiment, an integrated circuit having a substrate and active devices formed on the surface of the substrate. Other embodiments of the integrated circuit provide for having at least either three or four metal layers. In a particular embodiment of the present invention, the integrated circuit comprises a bond pad formed over a portion of the active devices. The bond pad has a footprint. As used therein the word footprint means the area covered by the device to which the word refers. The integrated circuit further incudes a patterned metal layer having a metal layer footprint that is located between the bond pad and the substrate and a built-in self-test (BIST) circuit that has a BIST footprint, which is located between the substrate and the bond pad. In this particular embodiment, the bond pad footprint overlays at least a portion of the metal layer footprint and the BIST footprint.

Abstract: A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an anti-reflective coating to prevent rainbowing or spiking of the coating into the underlying metal.

Abstract: Gate oxides having different thicknesses are grown on a semiconductor layer by the process which comprises forming a semiconductor layer on a substrate, growing an oxide layer on the semiconductor layer, exposing a selected area of the oxide layer, amorphizing the semiconductor layer underlying the exposed oxide layer, removing the oxide layer to expose the semiconductor layer having both amorphized and non-amorphized regions and growing gate oxide on the amorphized and non-amorphized regions of the semiconductor layer. Gate oxide grown on the amorphized regions will be thicker than gate oxide grown on the non-amorphized regions.The process of the invention obviates the need for special integrated circuit manufacturing design modifications and can be utilized to fabricate a wide variety of devices, in particular, MOS-type devices.

Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.

Abstract: A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an anti-reflective coating to prevent rainbowing or spiking of the coating into the underlying metal.

Abstract: A method of forming electromigration resistant integrated circuit runners is disclosed. A collimated beam of particles is directed toward a substrate to form a metal nucleating layer. Then a non-collimated beam is used to form the rest of the metal layer. Then the layers are patterned to form runners.

Abstract: A ROM (read only memory) is disclosed. For via-ROMs, an isolation transistor is used to isolate adjacent pairs of memory devices instead of the more conventional field oxide isolation. The gate of the isolation transistor is grounded, insuring that conduction does not take place. For a GASAD ROM, a field oxide isolation is used.

Abstract: A process for forming isolated active device regions on a silicon substrate comprises the steps of forming at least one trench in a silicon substrate to define at least two active device regions on the substrate to be isolated from each other, depositing an electrically insulative material on the substrate to fill the trench with the material, planarizing the surface of the substrate, performing a masking and etching operation to expose at least one active device region on the substrate, selectively growing a first epitaxial layer of silicon on the exposed active device region, masking the substrate to leave exposed at least one other active device region on the substrate, selectively growing a second epitaxial layer of silicon on the other exposed active device region, the first epitaxial layer and second epitaxial layer being doped with dopant atoms to the same or different dopant concentration to provide at least two isolated active device regions on the silicon substrate.

Abstract: Active circuitry is placed under the bond pads in an integrated circuit having at least three metal levels. The metal level adjacent the bond pad level acts as a buffer and provides stress relief and prevents leakage currents between the bond pad and underlying circuitry.

Abstract: Disclosed is a technique for forming integrated capacitors using a sequence of process steps that is fully compatible with standard silicon gate MOS integrated circuit processing. The capacitor comprises a polysilicon-oxide-TiN/metal combination. The lower plate, i.e. polysilicon plate, is interconnected at the gate level and the upper plate is interconnected typically at metal one.

Abstract: The base layer of high quality spacers, such as those used on the sidewalls of the gate stack of submicron devices (e.g., MOSFETs, EPROMs), are formed as composite, multi-layered structures of silicon oxides or of silicon oxides and silicon nitride.

Abstract: A method for etching metal conductors and stacks of conductors is disclosed. A doped silicon dioxide layer is deposited upon a metal or stack of conductive layers to be etched. A silicon dioxide layer is doped with phosphorous. Next, the silicon dioxide layer is partially etched and the photoresist removed. Subsequent etching utilizes the raised feature created in the silicon dioxide layer as a mask to etch the underlying metal or stack of conductors.