Abstract: A semiconductor device comprising a silicon-on-insulator (SOI) substrate including a base substrate, an insulator layer, and a silicon layer, a trench capacitor including at least one trench formed in the silicon-on-insulator substrate and extending through the silicon layer and the insulator layer to the base substrate, and a resistive element formed in the silicon-on-insulator substrate. The capacitor and resistor structure provide an R-C circuit which may be used in triggering an electrostatic discharge (ESD) protection device.

Abstract: A process for fabricating novel dual-polysilicon structures comprises forming trenches of differing depths in a field oxide that overlies a substrate. The trenches are formed using a stop layer so that the depth of the trenches may be precisely controlled. Utilizing an ion implantation barrier in the trenches, ion implantation is performed to create self-aligned structures. Importantly, polysilicon is formed in the trenches in a single deposition.

Abstract: A process for forming a dual damascene structure. The process includes forming a stack including insulating layers and a stop layer where two masks are formed above the stack. One of the masks is used to form via or contact openings in the insulating layers and the second mask is used to form grooves for interconnections in the insulating layers.

Abstract: A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.

Abstract: A method for forming a shallow trench isolation structure within a semiconductor substrate includes forming a trench opening within a semiconductor substrate having an oxidation-resistant material as a top surface. An oxide liner is formed on inner surfaces of the trench opening. A silicon material is then introduced into the trench opening and over the top surface. The silicon material is subsequently oxidized, either before or after a polishing operation is used to planarize the structure. Dishing related problems are avoided during polishing because the silicon or oxidized silicon material has a polishing rate similar to the oxidation resistant material, and less than that of conventionally formed CVD oxides.

Abstract: A new capacitor and a new method for fabricating the capacitor in an integrated circuit. The method uses fewer steps than those used in prior art processes. In accordance with the invention, trenches of differing depths are formed in a first insulating layer. One of the trenches is etched to expose a conducting layer formed under the insulating layer. Conductive material is deposited in the trenches to form a capacitor. The trenches are formed apart from each other.

Abstract: A process for fabricating novel dual-polysilicon structures comprises forming trenches of differing depths in a field oxide that overlies a substrate. The trenches are formed using a stop layer so that the depth of the trenches may be precisely controlled. Utilizing an ion implantation barrier in the trenches, ion implantation is performed to create self-aligned structures. Importantly, polysilicon is formed in the trenches in a single deposition.

Abstract: A method for forming tungsten plugs and layers is disclosed. A thin layer of polysilicon or amorphous silicon is formed within a contact opening. The silicon is exposed to WF6, thereby forming a tungsten plug.

Abstract: The present invention includes a method for reducing dishing of an integrated circuit interconnect, comprising the steps of providing excess interconnect material above a damascene feature in a substrate and planarizing the substrate and interconnect material to obtain an interconnect in the substrate.

Abstract: A process for forming a dual damascene structure. The process includes forming a stack including insulating layers and a stop layer where two masks are formed above the stack. One of the masks is used to form via or contact openings in the insulating layers and the second mask is used to form grooves for interconnections in the insulating layers. In an alternative embodiment, the grooves are formed before the via or contact openings.

Abstract: The specification describes techniques for wire bonding gold wires to copper metallization in semiconductor integrated circuits. A barrier layer is formed on the copper, and an aluminum bonding pad is formed on the barrier layer. Gold wire is then thermocompression bonded to the aluminum pad.

Abstract: An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent diffusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer.

Abstract: An insulating structure includes a first silicon nitride layer, a tantalum pentoxide layer formed above the first silicon nitride (SiNx) layer, and a second silicon nitride layer formed above the tantalum pentoxide (Ta2O5) layer. The SiNx cladding layers prevent difflusion of the tantalum during heating. A high dielectric constant is provided. The thermal stability of the insulating structure is improved. The insulating structure may be included in a capacitor or a shallow trench isolation structure. An exemplary capacitor is formed with a substrate, a lower electrode, the three-layer SixNy/Ta2O5/SixNy structure and an upper electrode. The lower electrode may include a TiN layer formed over an aluminum layer, or a TiN layer formed over a polysilicon layer, or a polysilicon layer having an oxide barrier layer formed on it. The upper electrode may be a TiN layer or a polysilicon layer.

Abstract: The invention includes a process for copper metallization of an integrated circuit, comprising the steps of forming tantalum on a substrate, forming tantalum nitride over the tantalum, forming titanium nitride over the tantalum nitride, forming copper over the titanium nitride and integrated circuits made thereby. The invention is particularly useful in forming damascene structures with large aspect ratios.

Abstract: A method and apparatus for in-line, non-contact depletion capacitance measurement of a semiconductor wafer using non-contact voltage measurement and non-contact surface photovoltage response.

Abstract: A system and method to more efficiently exchange information between a service provider, such as a semiconductor company, and its remote equipment units. The system capable of immediately handling a number of information items, each belonging to a different remote equipment unit is disclosed. The system includes a central controller configured for interfacing with a plurality of remote equipment units via a wireless network. The central controller is configured to receive information from each remote equipment unit via a wireless network. This information includes alarm conditions and corresponding requests for repair. Each of the remote equipment units is identified by a unique code which is included in the information transmitted to the computer to identity the source (i.e., identity of the transmitting remote equipment unit). The central controller uses the code of the transmitting remote equipment unit to retrieve the corresponding data record stored in its memory.

Abstract: A method for quality and reliability assurance testing a lot of fabricated ICs comprising the steps of testing the differential Iddq of a sample of ICs at a plurality of different voltages, burning-in a sample of ICs, and then testing the functionality of the sample of ICs. The method of the present invention enables the reliability of an entire lot of ICs to be tested by determining an effective screening voltage for differential Iddq testing of the ICs, thereby eliminating the need both to burn-in and conduct post burn-in testing of all future lots of the ICs. The method of the present invention also enables fabrication facilities and workers to be engaged in other tasks rather than testing of ICs.

Abstract: The present invention provides a bond pad support structure for use in an integrated circuit having a bond pad located thereon. In one embodiment, the bond pad support structure comprises a support layer that is located below the bond pad and that has an opening formed therein. The bond pad support structure further includes a dielectric layer that is located on the conductive layer and that extends at least partially into the opening to form a bond pad support surface over at least a portion of the opening. The first bond pad support layer, in one embodiment, may comprise a conductive metal and the second bond pad support layer may comprise of a dielectric material. The present invention provides a unique bond pad structure wherein an opening within a first bond pad support layer is at least partially filled with a second bond pad support layer.

Abstract: A method of forming a multi-layered dual-polysilicon structure that forms a polysilicon gate prior to formation of an ion implantation barrier and that requires fewer steps, is more economical, and permits fabrication of more compact semiconductor circuits and devices than prior art methods.

Abstract: A bond pad support structure is located beneath a bond pad on an integrated circuit. The bond pad support structure includes a first bond pad support layer at least partly located below the bond pad. The first bond pad support layer has a plurality of radial patterns with at least one space between the radial patterns. The radial patterns may be, for example, straight lines having approximately uniform thickness. Alternatively, the radial patterns may be triangles, each of which has an apex pointing to the center of a region below the bond pad. The radial patterns may have a plurality of different lengths. A second bond pad support layer is located on the first bond pad support layer. The second bond pad support layer fills at least a portion of the space between the radial patterns.