Patents by Inventor Sam Kyu Won

Sam Kyu Won has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10163523
    Abstract: A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc.
    Inventors: Sam Kyu Won, Myung Su Kim, Jae Won Cha
  • Publication number: 20180130544
    Abstract: A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 10, 2018
    Inventors: Sam Kyu WON, Myung Su KIM, Jae Won CHA
  • Patent number: 9899102
    Abstract: A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: February 20, 2018
    Assignee: SK Hynix Inc.
    Inventors: Sam Kyu Won, Myung Su Kim, Jae Won Cha
  • Publication number: 20160293271
    Abstract: A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.
    Type: Application
    Filed: November 27, 2015
    Publication date: October 6, 2016
    Inventors: Sam Kyu WON, Myung Su KIM, Jae Won CHA
  • Patent number: 9275745
    Abstract: A semiconductor device includes a memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages. A second storage unit loads a page address stored in the first storage unit. A control circuit is configured to cancel a program operation if an externally inputted page address is less than or equal to the page address loaded into the second storage unit, and perform the program operation and update the second storage unit with the externally inputted page address if the externally input page address is greater than the page address loaded into the second storage unit.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 1, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sam Kyu Won, Duck Ju Kim, Won Kyung Kang
  • Patent number: 9015392
    Abstract: A multi-chip package includes first and second semiconductor chips each configured to perform first and second operations having different current consumptions. The first and second semiconductor chips perform the first operation in response to an enable control signal transmitted from one of the first and second semiconductor chips to the other and transmitted from the other back to the one.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: April 21, 2015
    Assignee: SK Hynix Inc.
    Inventors: Won-Kyung Kang, Sam-Kyu Won
  • Patent number: 9013945
    Abstract: A memory system includes first to third memory devices each having an input terminal for receiving a token signal and an output terminal for transmitting the token signal, wherein the input terminal of each of the first to third memory devices are connected to the output terminal of another memory device through a ring topology, a subset of the first to third memory devices substantially simultaneously perform an operation of consuming a peak current in response to any one of a plurality of token signals, and each of the first to third memory devices possesses only any one of the plurality of token signals and transmits the other token signals to another memory device.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: April 21, 2015
    Assignee: SK Hynix Inc.
    Inventors: Sam Kyu Won, Sung Hyun Jung
  • Patent number: 8908462
    Abstract: The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 9, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sam Kyu Won, Cheul Hee Koo, Duck Ju Kim, Won Kyung Kang
  • Publication number: 20140258611
    Abstract: A semiconductor device includes a memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages. A second storage unit loads a page address stored in the first storage unit. A control circuit is configured to cancel a program operation if an externally inputted page address is less than or equal to the page address loaded into the second storage unit, and perform the program operation and update the second storage unit with the externally inputted page address if the externally input page address is greater than the page address loaded into the second storage unit.
    Type: Application
    Filed: July 3, 2013
    Publication date: September 11, 2014
    Inventors: Sam Kyu WON, Duck Ju KIM, Won Kyung KANG
  • Publication number: 20140160864
    Abstract: The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line.
    Type: Application
    Filed: March 18, 2013
    Publication date: June 12, 2014
    Applicant: SK hynix Inc.
    Inventors: Sam Kyu WON, Cheul Hee KOO, Duck Ju KIM, Won Kyung KANG
  • Publication number: 20140010033
    Abstract: A memory system includes first to third memory devices each having an input terminal for receiving a token signal and an output terminal for transmitting the token signal, wherein the input terminal of each of the first to third memory devices are connected to the output terminal of another memory device through a ring topology, and the first to third memory devices substantially simultaneously perform an operation of consuming a peak current in response to any one of a plurality of token signals.
    Type: Application
    Filed: December 11, 2012
    Publication date: January 9, 2014
    Applicant: SK hynix Inc.
    Inventors: Sam Kyu WON, Sung Hyun JUNG
  • Publication number: 20130307611
    Abstract: A multi-chip package includes first and second semiconductor chips each configured to perform first and second operations having different current consumptions. The first and second semiconductor chips perform the first operation in response to an enable control signal transmitted from one of the first and second semiconductor chips to the other and transmitted from the other back to the one.
    Type: Application
    Filed: August 10, 2012
    Publication date: November 21, 2013
    Inventors: Won-Kyung KANG, Sam-Kyu WON
  • Publication number: 20130080830
    Abstract: A setting data storage circuit includes a setting data storage block configured to store setting data; an access unit configured to access the setting data of the setting data storage block; an error detection unit configured to detect an error in the setting data; and an error recovery unit configured to recover an error in the setting data storage block when the error detection unit detects an error.
    Type: Application
    Filed: July 16, 2012
    Publication date: March 28, 2013
    Applicant: SK HYNIX INC.
    Inventor: Sam-Kyu WON
  • Patent number: 8335118
    Abstract: A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: December 18, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae Won Cha, Sam Kyu Won, Kwang Ho Baek
  • Patent number: 8218368
    Abstract: A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: July 10, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sam Kyu Won, Jae Won Cha, In Ho Kang, Kwang Ho Baek
  • Patent number: 8159883
    Abstract: A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell block when the semiconductor memory device operates. The semiconductor memory device includes a memory cell block in which a plurality of memory cells, drain and source select transistors, and side word line transistors are connected in a string structure, a block decoder for outputting a block select signal in response to predecoded address signals and controlling the drain and source select transistors and the side word line transistors, and a block switch for connecting a global word line to word lines of the memory cell block in response to the block select signal.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: April 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwang Ho Baek, Sam Kyu Won, Jae Won Cha
  • Patent number: 8125828
    Abstract: A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: February 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jin Yong Seong, Sam Kyu Won
  • Patent number: 8107297
    Abstract: A method of reading a nonvolatile memory device may include, after an nth erase operation is performed, reading dummy cells on which a program operation has been performed based on a first read voltage, where n is an integer greater than zero, counting a number of dummy cells that are read as having a threshold voltage lower than the first read voltage, when the number is a critical value or more, resetting a read voltage, and performing, based on the reset read voltage, a read operation on memory cells that belong to the same memory cell block as the dummy cells and on which a program operation has been performed on the memory cells after the nth erase operation has been performed.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: January 31, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwang Ho Baek, Sam Kyu Won
  • Patent number: 8085602
    Abstract: A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: December 27, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang Won Yang, Cheul Hee Koo, Sam Kyu Won
  • Publication number: 20110128783
    Abstract: A method of reading a nonvolatile memory device may include, after an nth erase operation is performed, reading dummy cells on which a program operation has been performed based on a first read voltage, where n is an integer greater than zero, counting a number of dummy cells that are read as having a threshold voltage lower than the first read voltage, when the number is a critical value or more, resetting a read voltage, and performing, based on the reset read voltage, a read operation on memory cells that belong to the same memory cell block as the dummy cells and on which a program operation has been performed on the memory cells after the nth erase operation has been performed.
    Type: Application
    Filed: February 9, 2011
    Publication date: June 2, 2011
    Inventors: Kwang Ho BAEK, Sam Kyu Won