Abstract: A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.

Abstract: A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the first verifying operation until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage; and performing a second verifying operation on the main cells and the indicator cells based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage.

Abstract: A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation.

Abstract: A method of reading a nonvolatile memory device may include, after an nth erase operation is performed, reading dummy cells on which a program operation has been performed based on a first read voltage, where n is an integer greater than zero, counting a number of dummy cells that are read as having a threshold voltage lower than the first read voltage, when the number is a critical value or more, resetting a read voltage, and performing, based on the reset read voltage, a read operation on memory cells that belong to the same memory cell block as the dummy cells and on which a program operation has been performed on the memory cells after the nth erase operation has been performed.

Abstract: A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.

Abstract: A method of programming a multi level cell in a non-volatile memory device includes: performing a program operation on main cells and indicator cells; performing a first verifying operation on the main cells and the indicator cells based on a first verifying voltage; performing repeatedly the program operation and the first verifying operation until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage; and performing a second verifying operation on the main cells and the indicator cells based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage.

Abstract: A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.

Abstract: A method for performing erasing operation in a nonvolatile memory device includes the steps of applying an erasing voltage to P-wells of a selected memory cell block which is composed of a plurality of strings in each of which a plurality of memory cells and side memory cells are connected in series; performing soft programming operation by applying a soft programming voltage to word lines of the selected memory cell block; and programming the side memory cells by applying a programming voltage to the side memory cells.

Abstract: A method of programming a multi level cell in a non-volatile memory device includes providing different data to main cells and indicator cells. The main cells and indicator cells have different threshold voltages in accordance with the data. A program operation is performed on a main cell and an indicator cell. A first verifying operation is performed based on a first verifying voltage of the main cell and the indicator cell. The program operation and the first verifying operation are performed repeatedly until a threshold voltage of a first cell of the indicator cells is higher than the first verifying voltage. A second verifying operation is performed on the main cell based on a second verifying voltage when the threshold voltage of the first cell is higher than the first verifying voltage.

Abstract: In a method of operating a non-volatile memory device, a bit line is precharged to a positive voltage, which is input through a common source line of cell strings of memory cells, according to a degree in which a selected memory cell has been programmed. Data according to a voltage level of a sensing node, which is changed according to a level of the voltage of the bit line, is stored in a first latch of a page buffer. The data stored in the first latch is transferred to a second latch through the sensing node.

Abstract: In a programming method of a non-volatile memory device, a program operation is performed by applying a program voltage to a selected word line and a first pass voltage to unselected word lines. The first pass voltage shifts to a second pass voltage having a level lower than that of the first pass voltage. A verify operation is performed by applying a verify voltage to the selected word line. The verify voltage has a level lower than that of the second pass voltage.

Abstract: A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.

Abstract: A method of operating a flash memory device includes reading a first bit data by employing a first read voltage or a second read voltage higher than the first read voltage according to a program state of a first flag cell. The first flag cell is programmed when the first bit data is programmed into the MLC. A second bit data may be read by employing a third read voltage that is higher than the first read voltage or the second read voltage, or by employing the first read voltage and the third read voltage according to a program state of a second flag cell. The second flag cell is programmed when the second bit data is programmed into the MLC. Alternatively to reading the second bit data, the second bit data is fixed to a set data and the set data is output.

Abstract: A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller.

Abstract: A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.

Abstract: In a method of determining a flag state of a non-volatile memory device, an arithmetic logic unit of a microcontroller is employed without an additional circuit. The method includes providing n flag state information about n flag cells, resetting an entire flag state information value, sequentially reading first to n flag state information, increasing the entire flag state information value depending on a read result of the first to n flag state information, and determining a flag state by comparing the entire flag state information value and a critical value.

Abstract: A voltage conversion circuit includes a reference voltage generation unit for generating a reference voltage having a uniform level regardless of a level of an input voltage varying according to an operation mode; and a driver unit for generating and outputting an active voltage or a standby voltage using the reference voltage output by the reference voltage generation unit according to a control signal.

Abstract: A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller.

Abstract: A nonvolatile memory device of a nonvolatile memory device includes a memory cell unit comprising sets of memory cells, a first supplementary information repository comprising source-side dummy cells respectively connected between source select transistors and first memory cells of the sets of the memory cells, and a second supplementary information repository comprising drain-side dummy cells respectively connected between drain select transistors and second memory cells of the sets of the memory cells.

Abstract: A method of reading a nonvolatile memory device may include, after an nth erase operation is performed, reading dummy cells on which a program operation has been performed based on a first read voltage, where n is an integer greater than zero, counting a number of dummy cells that are read as having a threshold voltage lower than the first read voltage, when the number is a critical value or more, resetting a read voltage, and performing, based on the reset read voltage, a read operation on memory cells that belong to the same memory cell block as the dummy cells and on which a program operation has been performed on the memory cells after the nth erase operation has been performed.