Abstract: A semiconductor memory device includes a high voltage generator for generating a high voltage and applying the generated high voltage to a memory unit, a converter for converting an output voltage of the high voltage generator into a digital signal, and a mode selection unit for outputting an output of the converter or an output of the memory unit through an I/O terminal selectively.

Abstract: A method of controlling a copy-back operation of a flash memory device including multi-level cells. In the method, the copy-back operation can be executed even without an additional storage space. Accordingly, a program time can be shortened and operational performance of a flash memory device can be improved.

Abstract: Non-volatile memory devices may include a buffer memory corresponding to one block of a memory cell array, thus improving a read operation. The non-volatile memory device may include a memory cell array including a plurality of memory blocks, each having memory cells disposed at the intersections of bit lines and word lines, a plurality of page buffers connected to the bit lines through a sensing line, and a buffer memory connected between the plurality of memory blocks and the plurality of page buffers. The buffer memory may include special buffers for storing the same data as those of the memory cells.

Abstract: An oscillator of a semiconductor memory device, wherein a reference voltage that flexibly shifts according to the shift in a power supply voltage is generated, and a reference clock is generated using the reference voltage. It is thus possible to generate the reference clock having a constant cycle regardless of the shift in the power supply voltage which can keep constant the duration period of internal control signals of devices, such as a timer and a pump circuit, which are synchronized to the reference clock.

Abstract: The present invention relates to a page buffer circuit with a reduced size, and a flash memory device having the page buffer circuit and program operation method thereof. According to the present invention, a page buffer circuit can perform a program operation of a Multi-Level Cell (MLC) using a data verify circuit even without a data compare circuit. Accordingly, an occupation area can be reduced and the size of a flash memory device can also be reduced.

Abstract: Non-volatile memory devices may include a buffer memory corresponding to one block of a memory cell array, thus improving a read operation. The non-volatile memory device may include a memory cell array including a plurality of memory blocks, each having memory cells disposed at the intersections of bit lines and word lines, a plurality of page buffers connected to the bit lines through a sensing line, and a buffer memory connected between the plurality of memory blocks and the plurality of page buffers. The buffer memory may include special buffers for storing the same data as those of the memory cells.

Abstract: Disclosed is a method of the present invention relates to a high voltage transfer circuit. The high voltage transfer circuit includes a first high voltage switch for transferring a high voltage generated within a chip to the outside of the chip according to a clock signal and a first control signal, and a second high voltage switch for transferring the high voltage generated outside the chip to the inside of the chip according to the clock signal and a second control signal. Therefore, it is possible to easily analyze fail of an initial product without manufacturing additional PMOS transistor that withstands a high voltage.

Abstract: Disclosed is a method of the present invention relates to a high voltage transfer circuit. The high voltage transfer circuit includes a first high voltage switch for transferring a high voltage generated within a chip to the outside of the chip according to a clock signal and a first control signal, and a second high voltage switch for transferring the high voltage generated outside the chip to the inside of the chip according to the clock signal and a second control signal. Therefore, it is possible to easily analyze fail of an initial product without manufacturing additional PMOS transistor that withstands a high voltage.

Abstract: A flash memory device according to the present invention comprises: a memory cell array having a plurality of memory cells; a dummy cell array having a plurality of dummy cells and connected to each word line of the memory cell array; a means for applying a voltage to a bit line of the dummy cell array; a level detector for detecting potential of the bit line in the dummy cell array; a row decoder for selecting a word line of the dummy cell array and the memory cell array according to an address signal; and a column decoder for selecting a bit line of the memory cell array according to the address signal; a sense amplifier enabled by an output of the level detector and for comparing data stored on the cell of the memory cell array with data stored on a reference cell.

Abstract: A flash memory device according to the present invention comprises: a memory cell array having a plurality of memory cells; a dummy cell array having a plurality of dummy cells and connected to each word line of the memory cell array; a loading means for applying a voltage to a bit line of the dummy cell array; a level detector for detecting potential of the bit line in the dummy cell array; a row decoder for selecting a word line of the dummy cell array and the memory cell array according to an address signal; and a column decoder for selecting a bit line of the memory cell array according to the address signal; a sense amplifier enabled by an output of the level detector and for comparing a data stored on the cell of the memory cell array with a data stored on a reference cell.

Abstract: A flash memory device includes a plurality of banks having a memory cell array and a row and column decoder, a system for classifying an input address into a read address and a write address depending on read or write operation, a first selecting system for enabling one of the plurality of the banks depending on the bank address allocated to the input address and the read address to perform the read operation, a second selecting system for enabling one of the plurality of the banks depending on the bank address allocated to the input address and the write address to perform the write operation, a sense amplifier for sensing data of the bank to compare them with data of a reference cell, and a pumping system for supplying a given bias to the bank.